M25P05-AVMN6T NUMONYX, M25P05-AVMN6T Datasheet - Page 21

• Manufacturer Part Number: M25P05-AVMN6T
• Description: IC FLASH 512KBIT 40MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 40MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1621-2

Figure 15. Page Program (PP) Instruction Sequence
Note: 1. Address bits A23 to A16 must be set to 00h.
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in
3.) is a valid address for the Sector Erase
S
C
D
S
C
D
MSB
7
40
0
6
41
1
5
42
Data Byte 2
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
Figure 16.
6
0
MSB
7
7
MSB
23
8
6
22 21
9 10
5
Data Byte 3
24-Bit Address
4
51
3
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
ration is t
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see
52 53 54 55
3
28 29 30 31 32 33 34 35
2
2
1
1
0
SE
Table 3.
0
) is initiated. While the Sector Erase cy-
MSB
7
MSB
7
6
6
and
5
Data Byte 1
Data Byte 256
5
4
Table
4
3
36 37 38
3
2
2
2.) is not executed.
1
1
0
39
AI04082B
0
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