CY7C1383C-100AC Cypress Semiconductor Corp, CY7C1383C-100AC Datasheet - Page 31

• Manufacturer Part Number: CY7C1383C-100AC
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1383C-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (1M x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1494-5

Document #: 38-05238 Rev. *B
Timing Diagrams
Read/Write Cycle Timing
Note:
21. On this diagram, when CE is LOW: CE
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC .
24. GW is HIGH.
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
(continued)
Q(A1)
A2
t ADH
[21, 23, 24]
t CEH
t
t AH
CH
t CYC
t
CL
1
Q(A2)
is LOW, CE
t
OEHZ
A3
2
is HIGH and CE
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
3
is LOW. When CE is HIGH: CE
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
X
LOW.
UNDEFINED
Q(A4+1)
BURST READ
1
is HIGH or CE
Q(A4+2)
2
is LOW or CE
Q(A4+3)
CY7C1381C
CY7C1383C
3
D(A5)
is HIGH.
A5
Back-to-Back
Page 31 of 36
WRITEs
D(A6)
A6