CY7C1383C-100AC Cypress Semiconductor Corp, CY7C1383C-100AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1383C-100AC
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1383C-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (1M x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1494-5

Document #: 38-05238 Rev. *B
CY7C1383C:Pin Definitions
ADSP
ADSC
ZZ
DQ
DQP
MODE
Name
s
[A:B]
69,72,73,8,9,12,
58,59,62,63,68,
18,19,22,23
Enable)
(3-Chip
TQFP
74,24
13,
84
85
64
31
P7,K7,G7,E7,F6
,H6,L6,N6,D1,H
1,L1,N1,E2,G2,
Enable)
(1-Chip
K2,M2
D6,P2
(continued)
BGA
A4
B4
R3
T7
F11,G11,J1,K1,
D2,E2,F2,
L10,M10,
J10,K10,
D11,E11,
Enable)
(3-Chip
C11,N1
L1,M1,
fBGA
H11
G2
B9
A8
R1
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Static
Input-
Input-
Input-
I/O-
I/O-
I/O
Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE
Address Strobe from Controller,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized .
ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O lines. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
in a tri-state condition. The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
controlled by BW
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
V
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
DD
1
s
. During write sequences, DQP
or left floating selects interleaved burst
is deasserted HIGH
Description
s
[A:B]
and DQP
correspondingly.
CY7C1381C
CY7C1383C
[A:B]
Page 10 of 36
are placed
[1:0]
[1:0]
[A:B]
are
are
is