CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet - Page 9

• Manufacturer Part Number: CY7C1367A-150AJC
• Description: IC SRAM 9MBIT 150MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 150MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1128

Document #: 38-05264 Rev. *A
Truth Table
Partial Truth Table for READ/WRITE
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Read
Read
Write Byte 0 – DQa
Write Byte 0 – DQb
Write Byte 1, 0
Write Byte 2 – DQc
Write Byte 2, 0
Write Byte 2, 1
Write Byte 2, 1, 0
Write Byte 3 – DQd
Notes:
10. For the X18 product, There are only BWa and BWb.
3.
4.
5.
6.
7.
8.
9.
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.
For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Function (1366)
Operation
[3, 4, 5, 6, 7, 8, 9]
Next
Next
External
External
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
Address Used CE CE
GW
1
1
1
1
1
1
1
1
1
1
[10]
H
H
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
L
L
L
L
BWE
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
1
0
0
0
0
0
0
0
0
0
2
CE
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
ADSP ADSC ADV WRITE OE
X
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
BWa
X
1
1
1
1
1
1
1
1
0
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
BWb
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
1
1
1
1
0
0
0
0
1
H
H
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
BWc
X
1
1
0
0
1
1
0
0
1
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Page 9 of 29
BWd
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
1
1
1
0
1
0
1
0
1
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D