CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet
CY7C1367A-150AJC
Specifications of CY7C1367A-150AJC
Related parts for CY7C1367A-150AJC
CY7C1367A-150AJC Summary of contents
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... North First Street • CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Pipelined SRAM and CY7C1367A/ Chip Enable input is only available 3 and CY7C1367A/ 7C1366A-166/ 7C1366A-150/ 71256C36-6 71256C36-6.7 7C1367A-166/ 7C1367A-150/ 71512C18-6 71512C18-6.7 3.5 3.5 425 380 San Jose CA 95134 • ...
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... TA version only. 3 Document #: 38-05264 Rev ter res ister ary nter & [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 DQa, DQb a c DQc, DQd DQa,D DQa, DQb, Qb Page ...
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... DQd DQd DQa DQd DQd DQd DQa CCQ CCQ CCQ CCQ DQd DQd DQd 53 DQa DQd DQd DQd DQa DQd DQd DQd DQa CY7C1367A/GVT71512C18 512K x 18 100- pin TQFP Top View CCQ CCQ CCQ CCQ DPa DPa DPa DQb 8 DQa DQa ...
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... ADSP CE A ADSC DQc DQc DQc DQc BWc ADV DQc DQd V CLK SS DQd BWd NC DQd V BWE SS DQd DQd MODE TMS TDI TCK CY7C1367A/GVT71512C18 512Kx18 119-Ball BGA Top View ADSP CE A ADSC DQb DQb BWb ADV DQb V CLK DQb V BWE DQb MODE ...
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... LOW or NC (No Connect). DQa Input/ Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb. DQb Output Third Byte is DQc. Fourth Byte is DQd. Input data must meet DQc set-up and hold times around the rising edge of CLK. DQd CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Page ...
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... Chip Enable: This active HIGH input is used to enable the 2 Synchronous device. CE Input- Chip Enable: This active LOW input is used to enable the 3 Synchronous device. Not available for B/BG and T/AJ package versions. OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Description Page ...
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... Power Output IEEE 1149.1 Test Output: LVTTL-level output. Not available for TA/A package version. V Power Supply Core Power Supply: +3.3V –5% and +10 Ground Ground: GND I/O Power Output Buffer Supply: +2.5V or +3.3V. CCQ Supply Connect: These signals are not internally connected. User can leave it floating or connect CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Page ...
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... Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW CY7C1367A) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. ...
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... Document #: 38-05264 Rev ADSP ADSC ADV WRITE [10] GW BWE BWa CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 CLK L-H High L-H High L-H High L-H High L-H High L L-H High L L L-H High L L-H High L L-H High L-H High L L-H High L L-H BWb BWc BWd Page ...
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... Test Access Port (TAP) TCK – Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 BWb BWc ...
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... Document #: 38-05264 Rev. *A CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay ...
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... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. 1149.1-mandatory Reserved Do not use these instructions. They are reserved for future use. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 plus Page The ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05264 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- [11] Page ...
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... I = 8.0 mA OLT [13 8.0 mA OHT /2; undershoot: V (AC) < –0.5V for t < t /2; power-up KHKH must not exceed V . Control input signals (such as R/W, ADV/LD) may not have pulse widths less than t CC CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 – ...
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... Test conditions are specified using the load in TAP AC Test Conditions. Document #: 38-05264 Rev. *A [16, 17] Over the Operating Range Description THTL THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Min. Max ALL INPUT PULSES 3.0V 1.5V 1.5 ns 1.5 ns (b) t TLTH ...
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... XXXXXX XXXXXX 00011100100 00011100100 1 1 Bit Size (x18 Description CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. Indicates the presence register. Page ...
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... Boundary Scan Order (512K × 18 Bit CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 (continued) Signal Name TQFP Bump ID DQc 1 2D DQc 2 1E DQc 3 2F DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K DQd 19 1L DQd 22 2M DQd 23 1N DQd 24 2P DQd ...
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... Boundary Scan Order (512K × 18) Bit# Signal Name TQFP 16 DQa 17 DQa ADV 22 ADSP 23 ADSC BWE CLK BWa 30 BWb 100 35 DQb 36 DQb 37 DQb 38 DQb DQb 41 DQb 42 DQb 43 DQb 44 DQb 45 MODE Document #: 38-05264 Rev. *A (continued) Bump CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Page ...
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... Device deselected; all inputs < > all inputs static MAX; CLK frequency = 0 CC Device deselected Max.; CC all inputs < 0.2 or >V – 0. CLK cycle time > t Min. KC CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Ambient [18 3.3V 2.5V-5%/3.3V –5%/+10% Min. Max. 2.0 5+0.5 2.0 1.7 –0.3 0.8 –0.3 0.7 5 – ...
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... V = 3.3V 2.8 CCQ V = 2.5V 2.8 CCQ [15, 25, 26] 0 [15, 25, 26] 2.5 [28] 1.5 [28] 0.5 is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Typ. Max TQFP Typ ALL INPUT PULSES V CCQ 90% 90% 10% 0V 1 -6.7 200 MHz 166 MHz 150 MHz Min ...
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... OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ , and CE are active CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Pull-down Current I (mA) Min. I (mA) Max Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ is only available for TA package version. 2 Page ...
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... ADSP# ADSP ADSC# ADSC t S ADDRESS A1 A BWa#, BWb#, BW BWc#, BWd#, x BWE BWE# GW# GW CE# CE ADV# ADV OE KQX DQ DQx Q SINGLE WRITE Document #: 38-05264 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Page D(A3+2) ...
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... S ADSP ADSP# ADSC ADSC ADDRESS A2 BW BWa#, BWb#, x BWE BWc#, BWd#, BWE#, GW# GW CE# CE ADV ADV# OE OE# DQx DQ Document #: 38-05264 Rev Q(A1) Q(A2) D(A3) Single Reads Single Write CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write Page ...
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... CE 1 LOW CE 2 HIGH I/Os 31. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 32. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05264 Rev ZZS I (active DDZZ Three-state CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 t ZZREC Page ...
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... CY7C1367A-200AJC/ GVT71512C18T-5 CY7C1367A-200AC/ GVT71512C18TA-5 CY7C1367A-200BGC/ GVT715152C18B-5 166 CY7C1367A-166AJC/ GVT715152C18T-6 CY7C1367A-166AC/ GVT71512C18TA-6 CY7C1367A-166BGC/ GVT71512C18B-6 150 CY7C1367A-150AJC/ GVT71512C18T-6.7 CY7C1367A-150AC/ GVT71512C18TA-6.7 CY7C1367A-150BGC/ GVT71512C18B-6.7 Document #: 38-05264 Rev. *A CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack BG119 119-Lead BGA ( ...
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... CY7C1367A-200AJCI/ GVT71512C18T-5I CY7C1367A-200ACI/ GVT71512C18TA-5I CY7C1367A-200BGCI/ GVT715152C18B-5I 166 CY7C1367A-166AJCI/ GVT715152C18T-6I CY7C1367A-166ACI/ GVT71512C18TA-6I CY7C1367A-166BGCI/ GVT71512C18B-6I 150 CY7C1367A-150AJC/ GVT71512C18T-6.7I CY7C1367A-150ACI/ GVT71512C18TA-6.7I CY7C1367A-150BGCI/ GVT71512C18B-6.7I Document #: 38-05264 Rev. *A CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack Industrial temp A101 100-Lead 1.4 mm Thin Quad Flat Pack BG119 119-Lead BGA ( ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05264 Rev. *A CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 51-85050-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead PBGA ( 2.4 mm) BG119 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 51-85115-*B Page ...
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... Document History Page Document Title: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Document Number: 38-05264 Orig. of REV. ECN No. Issue Date Change ** 114117 04/26/02 ** 125245 03/19/03 Document #: 38-05264 Rev. *A Description of Change KKV New Data Sheet IXR Changed KQ, KQX, KQLZ, KHZ, CY7C1366A/GVT71256C36 ...