CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet - Page 6

• Manufacturer Part Number: CY7C1367A-150AJC
• Description: IC SRAM 9MBIT 150MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 150MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1128

Document #: 38-05264 Rev. *A
256K × 36 Pin Descriptions
512K × 18 Pin Descriptions
3D, 5D, 3E, 5E, 3F,
5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N, 3P,
7J, 1M, 7M, 1U, 7U
1B, 7B, 1C, 7C, 4D,
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
3J, 5J, 4L, 1R, 5R,
1A, 7A, 1F, 7F, 1J,
4C, 2J, 4J, 6J, 4R
7R, 1T, 2T, 6T, 6U
X36 PBGA Pins
X18 PBGA Pins
(not available for
PBGA)
5T, 6T
4M
2U
3U
4U
5U
4N
3G
4H
5P
4P
4K
4E
2B
4F
5L
40, 55, 60, 67, 71,
80, 48, 47, 46, 45,
92 (T/AJ Version)
43 (TA/A Version)
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
100, 99, 82, 81,
X36 QFP Pins
X18 QFP Pins
35, 34, 33, 32,
15, 41,65, 91
38, 39, 42 for
for BG/B and
for BG/B and
TA/A Version
Version only)
92 (for TA/A
61, 70, 77
14, 16, 66
44, 49, 50
version
version
76, 90
T/AJ
T/AJ
38
39
43
42
37
36
93
94
87
88
89
98
97
86
(continued)
Name
V
Name
TMS
TCK
TDO Output Power IEEE 1149.1 Test Output: LVTTL-level output. Not available for
V
V
BWE
TDI
BWa
BWb
NC
CLK
CE
CE
CE
CCQ
GW
OE
A0
A1
CC
SS
A
1
2
3
Power Supply Core Power Supply: +3.3V –5% and +10%
I/O Power
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Ground
Supply
Type
Input
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Type
Input
–
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
TA/A package version.
Ground: GND.
Power supply for the circuitry.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set up and hold times around the rising
edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE
to occur independent of the BWE and WEn lines and must meet
the set up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Chip Enable: This active HIGH input is used to enable the
device.
Chip Enable: This active LOW input is used to enable the
device. Not available for B/BG and T/AJ package versions.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description
Description
CC
or V
SS
.
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