CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet - Page 10

• Manufacturer Part Number: CY7C1367A-150AJC
• Description: IC SRAM 9MBIT 150MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 150MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1128

Document #: 38-05264 Rev. *A
Partial Truth Table for READ/WRITE
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
Clock cycles are required to enter into or exit from this “sleep”
mode.
While in this mode, data integrity is guarantee. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep”
mode.CEs,ADSP, and ADSC must remain inactive for the
duration of t
ZZ Mode Electrical Characteristics
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
Write Byte 3, 0
Write Byte 3, 1
Write Byte 3, 1, 0
Write Byte 3, 2
Write Byte 3, 2, 0
Write Byte 3, 2, 1
Write All Byte
Write All Byte
Read
Read
I
t
t
DDZZ
ZZS
ZZREC
Write Byte 0 – DQ
Write Byte 0 – DQ
Write All Byte
Write All Byte
Parameter
Function (1366)
Function (1367)
ZZREC
after the ZZ inputs returns LOW.
[15:8]
[7:0]
and DP
and DP
Sleep mode stand-by current
Device operation to ZZ
ZZ recovery time
0
1
Description
GW
1
1
1
1
1
1
1
0
[10]
GW
1
1
1
1
1
0
(continued)
BWE
X
0
0
0
0
0
0
0
ZZ > V
ZZ > V
ZZ < 0.2V
Test Conditions
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (V
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to V
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK – Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
DD
DD
BWE
X
1
0
0
0
0
– 0.2V
– 0.2V
BWa
CC
X
0
0
0
0
0
0
0
through a resistor. TDO should be left unconnected.
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
2 t
BWb
Min.
X
1
1
1
0
0
0
0
cyc
BWb
X
X
1
1
0
0
BWc
2 t
Max
10
X
1
0
0
1
1
0
0
cyc
BWa
Page 10 of 29
X
1
0
1
0
x
BWd
Unit
mA
X
ns
ns
0
1
0
1
0
1
0
SS
) to