MT48H16M32LFCM-75 IT:A TR Micron Technology Inc, MT48H16M32LFCM-75 IT:A TR Datasheet - Page 27

• Manufacturer Part Number: MT48H16M32LFCM-75 IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M32LFCM-75 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 95mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1329-2

Figure 14:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
READ-to-WRITE
Notes:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on
page 26 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 15 on page 28 shows the case where the
additional NOP is needed.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated). The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with auto precharge. The disad-
vantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
1. CL = 3. The READ command may be to any bank, and the WRITE command may be to any
COMMAND
ADDRESS
bank. If a burst of one is used, then DQM is not required.
DQM
CLK
DQ
T0
BANK,
COL n
READ
T1
NOP
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
27
T2
NOP
t
RP is met. Note that part of the row precharge time is
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
t HZ
OUT
t CK
n
DON’T CARE
T4
BANK,
COL b
WRITE
D
IN
b
t
DS
©2005 Micron Technology, Inc. All rights reserved.
Operations