MT45W2MW16BGB-708 WT TR Micron Technology Inc, MT45W2MW16BGB-708 WT TR Datasheet - Page 14

• Manufacturer Part Number: MT45W2MW16BGB-708 WT TR
• Description: IC PSRAM 32MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1318-2

Figure 8:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
DQ[15:0]
LB#/UB#
Burst Mode READ (4-Word Burst)
A[20:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
Note:
The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to
indicate when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses the boundary between 128-word rows. After the Cellu-
larRAM device has restored the previous row’s data and accessed the next row, WAIT
will be deasserted and the burst can continue (see Figure 35 on page 46).
The processor can access other devices without incurring the timing penalty of the
initial latency for a new burst by suspending burst mode. Bursts are suspended by stop-
ping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus
while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM
outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be
active, and, as a result, no other devices should directly share the WAIT connection to
the controller. To continue the burst sequence, OE# is taken LOW, and then CLK is
restarted after valid data is available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
will cause CE# to remain LOW for longer than
burst restarted with a new CE# LOW/ADV# LOW cycle.
READ burst identified
Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
address
(WE# = HIGH)
t
CEM unless row boundaries are crossed at least every
Valid
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Latency code 2 (3 clocks)
14
D[0]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[1]
t
CEM, CE# should be taken HIGH and the
Don’t Care
D[2]
t
CEM. If a burst suspension
Bus Operating Modes
©2007 Micron Technology, Inc. All rights reserved.
D[3]
Undefined