MT45W2MW16BGB-708 WT TR Micron Technology Inc, MT45W2MW16BGB-708 WT TR Datasheet
MT45W2MW16BGB-708 WT TR
Specifications of MT45W2MW16BGB-708 WT TR
Related parts for MT45W2MW16BGB-708 WT TR
MT45W2MW16BGB-708 WT TR Summary of contents
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... DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 WAIT CLK ADV Top view (Ball down) Designator 1.0 specification of –25°C. 2. Contact factory for availability. Part Number Example: MT45W2MW16BGB-701WT ©2007 Micron Technology, Inc. All rights reserved. Features 6 None ...
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... Timing Requirements .36 Timing Diagrams .40 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Revision History .61 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zTOC.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2006 Micron Technology, Inc. All rights reserved. ...
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... Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Figure 49: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zLOF.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2007 Micron Technology, Inc. All rights reserved. ...
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... Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 16: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zLOT.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2007 Micron Technology, Inc. All rights reserved. ...
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... General Description Micron low-power, portable applications. The MT45W2MW16BGB is a 32Mb DRAM core device organized as 2 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases READ/WRITE bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...
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... Note: Functional block diagrams illustrate simplified device operation. See ball description table, bus operations tables, and timing diagrams for detailed information. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Address decode 2,048K x 16 logic DRAM memory ...
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... Upper byte enable: DQ[15:8]. WRITE enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or the memory array. Data inputs/outputs. Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE# ...
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... DPD is maintained until RCR is reconfigured. 8. CRE-controlled reading of the configuration register is supported for this device, though it is not an official CellularRAM 1.0 feature. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 CLK ADV# CE# OE# WE# L ...
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... DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. This device supports CRE-controlled configuration register READs. This feature is not an official CellularRAM 1.0 feature. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 CLK ADV# CE# OE# ...
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... To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory verify that the part number is offered and valid. If the Micron Technology, Inc ...
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... Functional Description In general, the MT45W2MW16BGB devices are high-density alternatives to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W2MW16BGB contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. ...
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... CE# OE# WE# Address Data LB#/UB# PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address Valid data READ cycle time < t CEM Valid address Valid data WRITE cycle time Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... The size of a burst can be specified in the BCR either as fixed-length or continuous. Fixed-length bursts consist words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device ...
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... The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data transferred into (or out of) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. After the Cellu- larRAM device has restored the previous row’s data and accessed the next row, WAIT will be deasserted and the burst can continue (see Figure 35 on page 46) ...
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... LB#/UB# Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address Latency code 2 (3 clocks) WRITE burst identified (WE# = LOW) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges ...
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... Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 Bus Operating Modes ...
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... Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 Bus Operating Modes ...
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... Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions either can start at the beginning or the end of the address map (see Table 6 on page 32) ...
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... WRITE operation when the configuration register enable (CRE) input is HIGH (see Figure 13, and Figure 14 on page 21). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[19:0 asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Latch control register address t CBPH Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... A19) Select register 1 A[19] CRE t VPH ADV# CE# OE# WE# LB#/UB# DQ[15:0] Note: A[19] = LOW to read RCR, HIGH to read BCR. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t AVH t AVS AVH t AVS AAVD Initiate register access OLZ ...
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... CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored—addi- tional WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Latch control register address t ABA t BOE t HD ...
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... Address CE# OE# WE# LB#/UB# Data Note possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or 0001h. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory READ READ WRITE ...
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... Address CE# OE# WE# LB#/UB# Data Note possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or 0001h. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory READ READ WRITE ...
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... Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 19 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] HIGH or through the configuration register software sequence with DQ = 0001h on the third cycle ...
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... PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 8-Word Burst Length 16-Word Burst Length ...
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... The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced- drive-strength option is included to minimize noise generated on the data bus during READ operations ...
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... Table 5: Latency Configuration Latency Configuration Code 2 (3 clocks clocks) – default PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory D[0] D[1] D[2] 104 MHz 66 (15ns) 104 (9.62ns) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... A[20:0] address ADV DQ[15: DQ[15: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Code 2 Valid output Code 3 (Default) 30 Configuration Registers Valid Valid Valid output output output Valid Valid Valid output output output Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array ...
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... Soldering temperature and time 10 seconds (solder ball only) Note: –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Active Section Address Space Full die 000000h–1FFFFFh One-half of die 000000h– ...
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... I SB inputs must be driven either to V after power-up, after changes to the PAR array partition, or when entering standby mode. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 (–30ºC < T < +85ºC); industrial temperature (–40ºC < Conditions Symbol ...
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... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16BGB device. The typical values shown in Figure 25 are measured with the default on-chip temperature sensor control enabled. Table 9: Partial-Array Refresh Specifications and Conditions ...
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... Output timing ends at V Figure 27: Output Load Circuit DUT Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Conditions 0V; +25° Conditions Symbol T = +25º ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The Low- Z timings measure a 100mV transition away from the High Page mode enabled only. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 Timing Requirements ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The Low- Z timings measure a 100mV transition away from the High PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 104 MHz Symbol Min t ABA – ...
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... OH 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The High-Z timings measure a 100mV transition either from V 3. WE# LOW time must be limited to PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory CEM (8µs). ...
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... CE# HIGH or CE# HIGH for greater than 15ns. Figure 28: Initialization Period Vcc, VccQ = 1.7V Table 16: Initialization Timing Parameters Parameter Initialization period (required before normal operations) PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 104 MHz Symbol Min t CBPH 5 t CEM – t ...
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... Timing Diagrams Figure 29: Asynchronous READ A[20:0] ADV# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address CE OLZ V t BLZ High CEW V OH High Timing Diagrams BHZ OHZ Valid output t HZ High-Z Don’ ...
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... Figure 30: Asynchronous READ Using ADV# A[20:0] ADV# LB#/UB# WE# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address VPH t AVS t AVH AADV CVS OLZ t BLZ High CEW V OH High Timing Diagrams ...
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... Figure 31: Page Mode READ A[20:4] A[3:0] ADV# LB#/UB# DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address Valid address CE OE OLZ WE BLZ Valid High-Z output CEW V OH High Timing Diagrams t RC Valid ...
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... READ burst identified (WE# = HIGH) Note: Nondefault BCR settings for single-access burst READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t ABA BOE ...
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... HIGH) Note: Nondefault BCR settings for 4-word burst READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t KHKL t CLK t CEM t ABA t BOE t OLZ ...
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... OL t ACLK Note: Nondefault BCR settings for READ burst suspend: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CEM t OHZ t KOH Valid Valid Valid ...
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... WAIT will be asserted a maximum of LC cycles (BCR[ WAIT asserted during delay latency code (BCR[13:11]). 3. CE# must not remain LOW longer than PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Note 3 t KHTL Note 2 Valid output t CEM ...
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... Figure 36: CE#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address CE OE WPH High WHZ V OH out CEW V OH High Timing Diagrams CPH Valid input ...
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... Figure 37: LB#/UB#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address CE OE WPH High WHZ out CEW V OH High Timing Diagrams Valid input t HZ High-Z Don’ ...
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... Figure 38: WE#-Controlled Asynchronous WRITE A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory CE OE WPH High WHZ out CEW V OH WAIT High Timing Diagrams t WC Valid address Valid input t OW ...
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... Figure 39: Asynchronous WRITE Using ADV# A[20:0] ADV# LB#/UB# DQ[15:0] DQ[15:0] WAIT PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH Valid address AVS t AVH VPH High WHZ out CEW V OH High Timing Diagrams WPH t WP ...
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... V IL WRITE burst identified (WE# = LOW) Note: Nondefault BCR settings for burst WRITE operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t KHTL D[0] Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... WAIT asserts. This differ- ence in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to abort on the start-of-row input cycle. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Note 4 t KHTL Note 3 Valid input ...
Page 53
... CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t SP Valid address t SP ...
Page 54
... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CKA Valid ...
Page 55
... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CKA Valid ...
Page 56
... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE clocked HIGH to terminate the burst. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK ABA t BOE ...
Page 57
... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE clocked HIGH to terminate the burst. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK VPH ABA ...
Page 58
... High-Z Data in/out Note: When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITEs. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address CPH High-Z Data CPH) to schedule the appropriate internal refresh operation. Otherwise, Micron Technology, Inc ...
Page 59
... IH High-Z Data in/out V IL Note: When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITEs. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Valid address AVS CVS t CPH WPH ...
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... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16BGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...
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... Changed A6 and A5 to “Ignored” and added the following text in Figure 24 on page 31: “Setting is ignored (default 00b).” Rev. A, Preliminary .02/07 • Initial release. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Q” in two instances in the diagram; revised note 2 to read, “Input timing begins Q/2.” CSP to SP ...