MT48H4M16LFB4-10 TR Micron Technology Inc, MT48H4M16LFB4-10 TR Datasheet - Page 21

• Manufacturer Part Number: MT48H4M16LFB4-10 TR
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
COMMAND
ADDRESS
Figure 19: Random WRITE Cycles
CLK
DQ
COMMAND
Each WRITE command may be to any bank.
DQM is LOW.
Figure 20: WRITE to READ
The WRITE command may be to any bank,
and the READ command may be to any bank.
DQM is LOW. CAS latency = 2 for illustration.
ADDRESS
WRITE
BANK,
COL n
D
T0
n
IN
CLK
DQ
n + 1
NOP
BANK,
WRITE
COL n
T1
D
D
IN
T0
n
IN
BANK,
READ
COL b
T2
WRITE
BANK,
COL a
T1
D
a
IN
T3
NOP
WRITE
BANK,
COL x
D
T2
x
IN
DON’T CARE
NOP
D
T4
OUT
WRITE
COL m
b
BANK,
T3
D
m
IN
DON’T CARE
NOP
b + 1
T5
D
OUT
21
NOTE:
PRECHARGE
CHARGE Command, on page 22) is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access some specified time (
charge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in
the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
t
COMMAND
COMMAND
t
WR @
WR @
The PRECHARGE command (see Figure 24, PRE-
ADDRESS
ADDRESS
Figure 21: WRITE to PRECHARGE
DQM
DQM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CLK
t
CK < 15ns
DQ
DQ
CK 15ns
DQM could remain LOW in this example if
the WRITE burst is a fixed length of two.
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
WR
PRECHARGE
(a or all)
BANK
NOP
T2
t
MOBILE SDRAM
WR
PRECHARGE
©2003 Micron Technology, Inc. All rights reserved.
(a or all)
BANK
T3
NOP
t RP
t
64Mb: x16
NOP
NOP
RP) after the pre-
T4
t RP
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6