MT48H4M16LFB4-10 TR Micron Technology Inc, MT48H4M16LFB4-10 TR Datasheet - Page 14

• Manufacturer Part Number: MT48H4M16LFB4-10 TR
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) refresh in conventional DRAMs. This command
is non persistent, so it must be issued each time a
refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum
PRECHARGE command as shown in the operation sec-
tion.
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (
command every 15.625µs will meet the refresh
requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
once every 64ms.
SELF REFRESH
data in the SDRAM, even if the rest of the system is
powered down, as long as power is not completely
removed from the SDRAM. When in the self refresh
mode, the SDRAM retains data without external clock-
ing. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). Once the SELF REFRESH command is regis-
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
AUTO REFRESH is used during normal operation of
The addressing is generated by the internal refresh
The SELF REFRESH command can be used to retain
t
REF). Providing a distributed AUTO REFRESH
t
RP has been met after the
t
RFC),
14
tered, all the inputs to the SDRAM become “Don’t
Care” with the exception of CKE, which must remain
LOW.
vides its own internal clocking, causing it to perform
its own auto refresh cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
t
inite period beyond that.
sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for
pletion of any internal refresh in progress.
commands should be issued at once and then every
15.625µs or less, as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
Deep Power-Down
maximum power reduction by eliminating the power
of the whole memory array of the device. Array data
will not be retained once the device enters deep
power-down mode.
CS# and WE# held low with RAS# and CAS# held high
at the rising edge of the clock, while CKE is low. This
mode is exited by asserting CKE high.
RAS and may remain in self refresh mode for an indef-
Once self refresh mode is engaged, the SDRAM pro-
The procedure for exiting self refresh requires a
Upon exiting the self refresh mode, AUTO REFRESH
The operating mode deep power-down achieves
This mode is entered by having all banks idle then
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
XSR because time is required for the com-
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16