MT48H8M32LFB5-8 IT TR Micron Technology Inc, MT48H8M32LFB5-8 IT TR Datasheet - Page 34
![IC SDRAM 256MBIT 8NS 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48H8M32LFB5-8 IT TR
Manufacturer Part Number
MT48H8M32LFB5-8 IT TR
Description
IC SDRAM 256MBIT 8NS 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48V8M32LFB5-8_IT_TR.pdf
(75 pages)
Specifications of MT48H8M32LFB5-8 IT TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
8ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1053-1
MT48H8M32LFB5-8 IT
MT48H8M32LFB5-8 IT
Figure 21: WRITE to PRECHARGE
PRECHARGE
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Note:
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
The PRECHARGE command (see Figure 23) is used to deactivate the open row in a par-
ticular bank or the open row in all banks. The bank(s) will be available for a subsequent
row access some specified time (
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated prior to any READ or WRITE com-
mands being issued to that bank.
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
COMMAND
COMMAND
t
t
WR@
WR@
ADDRESS
ADDRESS
DQM
DQM
t
t
CLK
CK ≥ 15ns
CK < 15ns
DQ
DQ
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
T1
34
D
D
IN
IN
t
RP) after the precharge command is issued. Input A10
t
WR
PRECHARGE
(a or all)
BANK
NOP
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR
PRECHARGE
(a or all)
BANK
T3
NOP
t RP
256Mb: x32 Mobile SDRAM
NOP
NOP
T4
t RP
©2003 Micron Technology, Inc. All rights reserved.
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
Operation