MT48H8M32LFB5-8 IT TR Micron Technology Inc, MT48H8M32LFB5-8 IT TR Datasheet - Page 10
![IC SDRAM 256MBIT 8NS 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48H8M32LFB5-8 IT TR
Manufacturer Part Number
MT48H8M32LFB5-8 IT TR
Description
IC SDRAM 256MBIT 8NS 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48V8M32LFB5-8_IT_TR.pdf
(75 pages)
Specifications of MT48H8M32LFB5-8 IT TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
8ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1053-1
MT48H8M32LFB5-8 IT
MT48H8M32LFB5-8 IT
Burst Length
Burst Type
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 3. The burst length determines the maximum num-
ber of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 4.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Register Definition