AT45DB321D-SU Atmel, AT45DB321D-SU Datasheet - Page 3
![IC FLASH 32MBIT 66MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
AT45DB321D-SU
Manufacturer Part Number
AT45DB321D-SU
Description
IC FLASH 32MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Datasheet
1.AT45DB321D-MU.pdf
(57 pages)
Specifications of AT45DB321D-SU
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
32M (8192 pages x 528 bytes)
Speed
66MHz
Interface
SPI, RapidS
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Package
8SOIC EIAJ
Density
32 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 64
Timing Type
Synchronous
Interface Type
Serial-SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
528 B x 8192
Memory Configuration
8192 Pages X 528 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT45DB321D-SU
Manufacturer:
ATMEL
Quantity:
15 000
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AT45DB321D-SU
Manufacturer:
ATMEL
Quantity:
1 000
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Part Number:
AT45DB321D-SU
Manufacturer:
Atmel
Quantity:
7 530
Company:
Part Number:
AT45DB321D-SU
Manufacturer:
ATMEL
Quantity:
3
Part Number:
AT45DB321D-SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Part Number:
AT45DB321D-SU-2.5
Manufacturer:
ON
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Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 2-1.
3597O–DFLASH–10/09
Symbol
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
V
GND
CC
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device
will be deselected and normally be placed in the standby mode (not Deep Power-Down mode),
and the output pin (SO) will be in a high-impedance state. When the device is deselected, data
will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such as
a program or erase cycle, the device will not enter the standby mode until the completion of the
operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always
clocked out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of whether
the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle state
once the CS pin has been deasserted. The Enable Sector Protection command and Sector
Lockdown command, however, will be recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long as
a low level is present on the RESET pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
Ready/Busy: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through an external
pull-up resistor), will be pulled low during programming/erase operations, compare operations,
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Device Power Supply: The V
Operations at invalid V
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
Pin Configurations
CC
voltages may produce spurious results and should not be attempted.
CC
pin is used to supply the source voltage to the device.
CC
AT45DB321D
Asserted
State
Low
Low
Low
–
–
–
–
–
–
Ground
Output
Output
Power
Type
Input
Input
Input
Input
Input
3