DS28EC20+ Maxim Integrated Products, DS28EC20+ Datasheet - Page 5

• Manufacturer Part Number: DS28EC20+
• Description: IC EEPROM 20KBIT TO92-3
• Manufacturer: Maxim Integrated Products

Specifications of DS28EC20+

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 20K (256 x 80)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: TO-92-3 (Standard Body), TO-226
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

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maximum duration for the master to pull the line low is t
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V
data line, 2.5µs after V
Guaranteed by design, characterization and/or simulation only. Not production tested.
V
capacitive loading on I/O. Lower V
and V
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to V
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After V
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
Defines maximum possible bit rate. Equal to 1/(t
Interval after t
limit is t
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
of the bus master. The actual maximum duration for the master to pull the line low is t
Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to V
impedance bypass of R
The t
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
Write-cycle endurance is degraded as T
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
TL
, V
PROG
TH
HY
TH
PDHMAX
, and V
.
is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V
interval begins t
; maximum limit is t
RSTL
HY
are a function of the internal supply voltage which is itself a function of V
during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum
PUP
PUP
REHMAX
has been applied the parasite capacitance does not affect normal communications.
PROG
, which can be activated during programming, is required.
to I
A
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
PDHMIN
increases.
L
PUP
.
, higher R
+ t
A
PDLMIN
increases.
.
PUP
W0LMIN
ILMAX
, shorter t
at all times the master is driving I/O to a logic 0 level.
+ t
5 of 27
W1LMAX
RECMIN
REH
REC
after V
+ t
).
, and heavier capacitive loading all lead to lower values of V
F
- ε and t
PUPMIN
TH
PUP
has been reached on the preceding rising edge.
. For 3.3V±5% V
is first applied. If a 2.2kΩ resistor is used to pull up the
W0LMAX
+ t
F
- ε, respectively.
RLMAX
PUP
PUP
+ t
HY
operation of the DS28EC20, a low-
, R
F
to be detected as logic 0.
.
PUP
, 1-Wire timing, and
IL
IL
to V
to the input high threshold
TH
. The actual
TL
, V
TH
,