DS28EC20+ Maxim Integrated Products, DS28EC20+ Datasheet - Page 3

• Manufacturer Part Number: DS28EC20+
• Description: IC EEPROM 20KBIT TO92-3
• Manufacturer: Maxim Integrated Products

Specifications of DS28EC20+

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 20K (256 x 80)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: TO-92-3 (Standard Body), TO-226
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Note 25:
* Intentional change, longer recovery time requirement due to modified 1-Wire front-end.
# For operation at overdrive speed, the DS28EC20 requires V
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance) (Notes 21,
22)
Data Retention
(Notes 23, 24, 25)
t
PARAMETER
SLOT
PARAMETER
(incl. t
t
t
t
t
RSTL
PDH
W0L
PDL
Specifications at T
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V
data line, 2.5µs after V
Guaranteed by design, characterization and/or simulation only. Not production tested.
V
capacitive loading on I/O. Lower V
and V
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to V
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After V
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
Defines maximum possible bit rate. Equal to 1/(t
Interval after t
limit is t
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
maximum duration for the master to pull the line low is t
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
of the bus master. The actual maximum duration for the master to pull the line low is t
Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by I
× R
minimum voltage requirements for programming.
The t
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
Write-cycle endurance is degraded as T
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
TL
, V
PUP
REC
PROG
TH
HY
TH
below V
PDHMAX
)
, and V
.
is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V
interval begins t
; maximum limit is t
RSTL
HY
PUP
480µs
STANDARD SPEED
61µs
15µs
60µs
60µs
MIN
are a function of the internal supply voltage which is itself a function of V
during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum
. If V
A
= -40°C are guaranteed by design only and not production-tested.
PUP
SYMBOL
PUP
I
t
REHMAX
PROG
PROG
N
has been applied the parasite capacitance does not affect normal communications.
and R
PROG
t
(undefined)
(undefined)
DR
CY
240µs
120µs
MAX
60µs
to I
LEGACY VALUES
A
PUP
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
PDHMIN
increases.
PUP
L
.
are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design
, higher R
(Note 19)
(Note 20)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
+ t
A
increases.
PDLMIN
OVERDRIVE SPEED#
48µs
MIN
7µs
2µs
8µs
6µs
.
PUP
W0LMIN
ILMAX
, shorter t
CONDITIONS
at all times the master is driving I/O to a logic 0 level.
+ t
3 of 27
W1LMAX
(undefined)
RECMIN
REH
REC
MAX
80µs
24µs
16µs
6µs
after V
+ t
).
, and heavier capacitive loading all lead to lower values of V
F
PUP
- ε and t
TH
PUP
to be 5V ±5%.
has been reached on the preceding rising edge.
is first applied. If a 2.2kΩ resistor is used to pull up the
W0LMAX
STANDARD SPEED
480µs
65µs*
15µs
60µs
60µs
MIN
+ t
F
- ε, respectively.
RLMAX
200k
MIN
50k
(undefined)
DS28EC20: 20Kb 1-Wire EEPROM
40
DS28EC20 VALUES
640µs
240µs
120µs
PUP
MAX
60µs
+ t
HY
, R
F
to be detected as logic 0.
.
PUP
TYP
, 1-Wire timing, and
IL
IL
to V
to the input high threshold
OVERDRIVE SPEED#
48µs
8µs*
MIN
2µs
8µs
6µs
TH
. The actual
MAX
0.8
10
(undefined)
15.5µs
MAX
80µs
24µs
6µs
UNITS
years
TL
mA
ms
⎯
, V
PROG
TH
,