IDT7025L15PF IDT, Integrated Device Technology Inc, IDT7025L15PF Datasheet - Page 12

• Manufacturer Part Number: IDT7025L15PF
• Description: IC SRAM 128KBIT 15NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7025L15PF

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7025L15PF

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
NOTES:
1. R/W or CE or UB & LB = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = V
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
8. If OE = V
9. To access RAM, CE = V
CE or SEM
ADDRESS
CE or SEM
ADDRESS
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
UB or LB
DATA
(Figure 2).
placed on the bus for the required t
specified t
for either condition.
UB or LB
DATA
WR
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going to V
R/W
R/W
OUT
OE
IN
IN
(9)
(9)
IL
WP
(9)
(9)
during R/W controlled write cycle, the write pulse width must be the larger of t
.
IL
,
UB or LB
IL
IH
transition occurs simultaneously with or after the R/W = V
t
during all address transitions.
AS
t
AS
(6)
DW
EW
=
(6)
. If OE = V
or t
V
IL
,
(4)
WP
and SEM = V
) of a UB or LB = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
t
WZ
IH
.
To access Semaphore, CE = V
(7)
t
t
AW
AW
t
t
WC
WC
IL
and a CE = V
t
t
EW
WP
(2)
(2)
IH
6.42
12
to the end-of-write cycle.
IL
and a R/W = V
t
t
DW
DW
IL
Military, Industrial and Commercial Temperature Ranges
transition, the outputs remain in the HIGH impedance state.
IH
WP
or UB & LB
or (t
t
IL
WR
WZ
for memory array writing cycle.
(3)
+ t
=
V
t
DW
t
t
DH
WR
DH
IH
) to allow the I/O drivers to turn off and data to be
,
t
OW
and SEM = V
(3)
IL
t
.
HZ
t
EW
(7)
must be met
(4)
(1,5,8)
2683 drw 10
2683 drw 09
(1,5)