IDT71T75702S85PFG IDT, Integrated Device Technology Inc, IDT71T75702S85PFG Datasheet - Page 2

• Manufacturer Part Number: IDT71T75702S85PFG
• Description: IC SRAM 18MBIT 85NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71T75702S85PFG

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous ZBT
• Memory Size: 18M (512K x 36)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71T75702S85PFG

NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
I/O
I/O
ADV/
Symbol
A
V
P1
TMS
TDO
R/
CE
CLK
TCK
V
V
0
1
TDI
0
1
ZZ
DDQ
-A
,
-I/O
DD
SS
-
-I/O
2
19
31
P4
2
4
Linear Burst Order
Test Mode Select
Data Input/Output
Test Data Output
Advance / Load
Address Inputs
Individual Byte
Test Data Input
Power Supply
Power Supply
Write Enables
Output Enable
Pin Function
Clock Enable
Chip Enables
Read / Write
Sleep Mode
Chip Enable
JTAG Reset
Test Clock
(Optional)
Ground
Clock
N/A
N/A
N/A
I/O Active
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
HIGH Synchronous active high chip enable. CE
HIGH
LOW Synchronous Clock Enable Input. When
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
LOW Synchronous active low chip enable.
LOW Burst ord er selection input. When
LOW Asynchronous output enable.
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/
chip deselected, any burst in progress is terminated. When ADV/
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
R/
cycle later.
clock are ignored and outputs remain unchanged. The effect of
outputs is as if the low to high clock transition did not occur. For normal operation,
sampled low at rising edge of clock.
cycles (When R/
ignored when R/
later.
(
deselect cycle. The ZBT
deselect is initiated.
inverted polarity but otherwise identical to
made with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
low the Linear burst sequence is selected.
operation.
Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
Serial output of registers placed between TDI and TDO. This output is active d epending on the state of
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
Ground.
ADV/
when it is sampled low at the rising edge of clock with the chip selected. When ADV/
ADV/
Write access to the memory array. The data bus activity for the current cycle takes place one clock
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
This is the clock input to the IDT71T75702/902. Except for
the I/O pins are in a high-impedance state.
write cycles. In normal operation,
TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
the TAP controller.
This pin has an internal pulldown.
2.5V core power supply.
2.5V I/O Supply.
1
signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
or
is a synchronous input that is used to load the internal registers with new address and control
is sampled high.
1
-
2
can be left floating. This pin has an internal pullup. Only available in BGA package.
sampled high or CE
4
low,
can all be tied low if always doing write to the entire 36-bit word.
and ADV/
is sampled high. The appropriate byte(s) of data are written into the device one cycle
lo w, and true chip enables.
TM
6.42
has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after
2
are sampled low) the appropriate byte write signal (
2
must be low to read data from the IDT71T75702/902. When
sampled low) and ADV/
can be tied low.
is high the Interleaved burst sequence is selected. When
1
2
and
is used with
1
is sampled high, all other synchronous inputs, including
Description
and
does not need to be active ly controlled for read and
is a static input, and it must not change during device
Commercial and Industrial Temperature Ranges
2
are used with CE
2
.
1
and
, all timing refe rences for the device are
low at the rising edge of clock, initiates a
2
2
sampled high on the device
is sampled high then the internal
to enable the chip. CE
to enable the IDT71T75702/902
1
must be
-
is low with the
2
4
) must be
has
is HIGH
5319 tbl 02
is