IDT70V05L35J IDT, Integrated Device Technology Inc, IDT70V05L35J Datasheet - Page 18

• Manufacturer Part Number: IDT70V05L35J
• Description: IC SRAM 64KBIT 35NS 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V05L35J

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (8K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70V05L35J

Truth Table III — Interrupt Flag
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. V
3. Writes to the left port are internally ignored when BUSY
Truth Table V — Example of Semaphore Procurement Sequence
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O
3. CE = V
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
o N
L
i R
L
L
i R
L
i R
i R
L
L
C
f e
f e
f e
f e
f e
f e
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
h g
h g
h g
h g
X
X
R/W
H
L
E
pull, not open drain outputs. On slaves the BUSY
enable inputs of this port. If t
BUSY
P t
P t
P t
P t
P t
P t
A
L
X
X
X
IL
P t
P t
P t
P t
L
i t c
t r o
t r o
t r o
t r o
t r o
t r o
if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V
L
n o
t r o
t r o
t r o
t r o
R
C
W
W
W
W
W
W
IH
X
X
H
outputs are driving low regardless of actual logic level on the pin.
E
L
W
W
W
W
L
R
t i r
t i r
t i r
t i r
t i r
t i r
, SEM = V
R
= V
= V
n I
t i r
t i r
t i r
t i r
s e
s e
s e
s e
s e
s e
L
s e
s e
s e
s e
C
u p
and BUSY
IL
IL
X
X
E
L
L
" 0 "
" 1 "
" 0 "
" 1 "
" 0 "
" 1 "
u F
, then no change.
, then no change.
s t
L
" 0 "
" 1 "
" 0 "
" 1 "
L
N
c n
A
A
= BUSY
O
o t
o t
o t
o t
o t
o t
M
M
M
1
IL
1
o t
o t
o t
o t
R 2
o i t
L 2
A
A
A
M
e S
e S
e S
e S
e S
e S
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
C T
C T
C T
A -
A -
A
e S
e S
e S
e S
R
s n
m
m
m
m
m
m
C T
L
O
L 0
R 0
H
H
H
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY
t f e
m
m
m
m
R
p a
p a
p a
p a
p a
p a
X
X
X
L
E
H
p a
p a
p a
p a
= V
L
APS
o h
o h
o h
o h
o h
o h
P
o h
o h
o h
o h
o
IH
e r
e r
e r
e r
e r
e r
is not met, either BUSY
t r
.
e r
e r
e r
e r
B
U
A
S
) 2 (
H
H
H
1
F 1
F 1
Y
L 2
L
X
X
O
F F
E F
) 1 (
A -
t u
L 0
u p
B
s t
X
U
D
0
input internally inhibits writes.
and read from all I/O's (I/O
S
0
) 2 (
H
H
H
Y
-
N I
L
R
D
H
X
X
L
) 1 (
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
1
0
0
1
1
0
1
1
1
0
1
L
T
7
) 3 (
) 2 (
or BUSY
L
L
t f e
r W
F
e t i
/ R W
o N
o N
o N
R
n u
X
X
X
L
= LOW will result. BUSY
n I
m r
m r
m r
i t c
R
i h
9 2
(1)
D
n o
l a
l a
l a
t i b
1 4
0
l b t
) 3 (
-
D
6 1
0
7
C
1
1
1
0
0
1
1
0
1
1
1
-I/O
6.42
X
X
R
E
L
L
18
g i
R
7
). These eight semaphores are addressed by A
t h
R
O
e S
L
o N
i R
o N
L
e S
i R
e S
L
e S
g i
L
X
X
X
f e
f e
f e
E
L
h g
h g
and BUSY
t h
m
m
m
m
R
p t
p t
p t
c
h c
p a
p t
p a
p t
p a
p a
a h
P
r o
t r o
r o
n a
IH
o
o h
g n
t r o
o h
r o
o h
o h
h t
h t
e g
t r
if the inputs to the opposite port became stable after the address and
b o
h t
e r
. e
e r
e r
e r
s a
s a
b o
L .
Industrial and Commercial Temperature Ranges
A
a t
s a
R
r f
R
r f
r f
r f
1
a t
F 1
e s
s n i
e s
F 1
e e
f e
e e
e e
e e
R 2
outputs cannot be low simultaneously.
g i
s n i
e s
X
X
p t
m
m
E F
t h
A -
F F
e s
m
a
a
r o
R 0
i s
e s
h p
h p
a
m
e d
h t
h p
m
r o
a
r o
h p
s a
a
r o
t e
h
t e
h p
s a
t e
r o
o n
k o
k o
r o
t e
k o
N I
o n
n e
t e
n e
r w
H
X
X
L
k o
T
n e
) 2 (
) 3 (
r w
R
k o
e t i
S
n e
e t i
t a t
n e
c a
s u
0
c a
S
R
e S
e R
e c
-A
X
t e
s e
e c
2
outputs on the IDT70V05 are push
s s
L t
e s
.
t e
R
s s
t f e
L t
g i
o t
R
t h
o t
t f e
g i
N I
e s
N I
t h
e s
T
m
N I
F
L
T
N I
p a
m
T
n u
R
l F
L
T
p a
o h
l F
g a
i t c
R
l F
o h
g a
(1,2,3)
e r
l F
g a
n o
e r
g a
9 2
9 2
1 4
1 4
l b t
l b t
5 1
7 1