IDT7024S55J IDT, Integrated Device Technology Inc, IDT7024S55J Datasheet - Page 14
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IDT7024S55J
Manufacturer Part Number
IDT7024S55J
Description
IC SRAM 64KBIT 55NS 84PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT7024L15PFG.pdf
(22 pages)
Specifications of IDT7024S55J
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
64K (4K x 16)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7024S55J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT7024S55J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7024S55J
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT7024S55J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" Blocking R/W
3. t
Timing Waveform of Write with Port-to-Port Read and BUSY
DATA
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
WH
DATA
WB
ADDR
ADDR
BUSY
L
must be met for both BUSY input (slave) and output (master).
is only for the 'Slave' Version.
= CE
R/W
OUT "B"
IN "A"
IL
R
for the reading port.
"A"
"A"
"B"
"B"
IL
= V
(slave) then BUSY is an input BUSY
IL
.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
"A"
APS
= V
is ignored for M/S = V
IL
"B"
and BUSY
t
WB
goes HIGH.
(3)
t
"B"
BAA
= don't care, for this example.
MATCH
IL
6.42
14
t
(SLAVE).
t
WC
WP
(2)
Military, Industrial and Commercial Temperature Ranges
t
WP
t
DW
MATCH
t
WDD
VALID
t
WH
(1)
2740 drw 14
t
DDD
(3)
(2,4,5)
,
t
BDA
t
DH
(M/S = V
2740 drw 13
t
BDD
VALID
IH
)