PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 56

• Manufacturer Part Number: PSD4235G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1969

PLDS
16
56/129
PLDS
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs using PSDsoft Express, the logic is programmed into the device and available
upon Power-up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in the following
sections.
The DPLD performs address decoding for internal components, such as memory, registers,
and I/O ports Select signals.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft Express. An input Bus consisting of 82 signals is connected to the PLDs. The
signals are shown in
The Turbo bit in PSD
The PLDs in the PSD4235G2 can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit
to ’0’ (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turning the Turbo mode off increases propagation delays while reducing
power consumption. See
Additionally, five bits are available in the PMMR2 register to block MCU control signals from
entering the PLDs. This reduces power consumption and can be used only when these
MCU control signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Table 32.
MCU address bus
MCU control signals
Reset
Power-down
Port A input macrocells
Port B input macrocells
Port C input macrocells
Port D inputs
Port F inputs
Figure 11
DPLD and CPLD inputs
Input source
(1)
shows the configuration of the PLDs.
Table
Section 21: Power
32.
A15-A0
CNTL0-CNTL2
RST
PDN
PA7-PA0
PB7-PB0
PC7-PC0
PD3-PD0
PF7-PF0
management, on how to set the Turbo bit.
Input name
Number of
PSD4235G2
signals
16
3
1
1
8
8
8
4
8