PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 21

• Manufacturer Part Number: PSD4235G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1969

PSD4235G2
3
3.1
3.2
3.3
PSD architectural overview
PSD devices contain several major functional blocks.
PSD device family. The functions of each block are described briefly in the following
sections. Many of the blocks perform multiple functions and are user configurable.
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in
The 4 Mbit primary Flash memory is the main memory of the PSD. It is divided into 8
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector
is individually selectable.
The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM.
Each memory block can be located in a different address space as defined by the user. The
access times for all memory types includes the address latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD
(CPLD), as shown in
partitioning of the PLDs reduces power consumption, optimizes cost/performance, and
eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can
implement more general user-defined logic functions. The CPLD has 16 output macrocells
(OMC) and 8 combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can
be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD input Bus
and are differentiated by their output destinations, number of product terms, and macrocells.
The PLDs consume minimal power. The speed and power consumption of the PLD is
controlled by the Turbo bit in PMMR0 and other bits in PMMR2. These registers are set by
the MCU at run-time. There is a slight penalty to PLD propagation time when not in the
Turbo mode.
I/O ports
The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O
pin can be individually configured for different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed
address/data buses
The JTAG pins can be enabled on Port E for in-system programming (ISP).
Table
Section 7.1: Memory blocks on page
3, each optimized for a different function. The functional
Figure 3
shows the architecture of the
PSD architectural overview
35.
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