PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 32
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PSD4235G2-90UI
Manufacturer Part Number
PSD4235G2-90UI
Description
IC FLASH 4MBIT 90NS 80TQFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD4235G2-70U.pdf
(129 pages)
Specifications of PSD4235G2-90UI
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1969
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD4235G2-90UI
Manufacturer:
TI
Quantity:
8 802
Company:
Part Number:
PSD4235G2-90UI
Manufacturer:
STMicroelectronics
Quantity:
10 000
Register bit definition
6.16
Note:
32/129
APD Enable:
PLD Turbo:
PLD Array CLK:
PLD MCells CLK:
PMMR2 register
Table 24.
For bit 4, bit 3, bit 2: See
PLD Array Addr:
In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4).
PLD Array CNTL2:
PLD Array CNTL1
PLD Array CNTL0
PLD Array ALE
Bit 7
not used
(set to ’0’)
0: Automatic Power-down (APD) is disabled.
1: Automatic Power-down (APD) is enabled.
0: PLD Turbo is on.
1: PLD Turbo is off, saving power.
0: CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD
when Turbo bit is off.
1: CLKIN to the PLD AND array is disconnected, saving power.
0: CLKIN to the PLD macrocells is connected.
1: CLKIN to the PLD macrocells is disconnected, saving power.
0: Address A7-A0 are connected to the PLD array.
1 Address A7-A0 are blocked from the PLD array, saving power.
0: CNTL2 input to the PLD AND array is connected.
1: CNTL2 input to the PLD AND array is disconnected, saving power.
0: CNTL1 input to the PLD AND array is connected.
1: CNTL1 input to the PLD AND array is disconnected, saving power.
0: CNTL0 input to the PLD AND array is connected.
1: CNTL0 input to the PLD AND array is disconnected, saving power.
0: ALE input to the PLD AND array is connected.
1: ALE input to the PLD AND array is disconnected, saving power.
Bit 6
PLD
Array
WRH
PMMR2 register
Bit 5
PLD
Array ALE
Table 34
for the signals that are blocked on pins CNTL0-CNTL2.
Bit 4
PLD Array
CNTL2
Bit 3
PLD Array
CNTL1
Bit 2
PLD Array
CNTL0
Bit 1
not used
(set to ’0’)
PSD4235G2
Bit 0
PLD
Array Addr