IDT7130LA100P IDT, Integrated Device Technology Inc, IDT7130LA100P Datasheet - Page 9
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IDT7130LA100P
Manufacturer Part Number
IDT7130LA100P
Description
IC SRAM 8KBIT 100NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Specifications of IDT7130LA100P
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
100ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Density
8Kb
Access Time (max)
100ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
110mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
48
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130LA100P
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT7130LA100P
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT7130LA100PF
Manufacturer:
IDT
Quantity:
1 831
Company:
Part Number:
IDT7130LA100PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7130LA100PF
Manufacturer:
IDT
Quantity:
20 000
Timing Waveform of Read Cycle No. 1, Either Side
NOTES:
1. R/W = V
2. t
3. Start of valid data depends on which timing becomes effective last t
Timing Waveform of Read Cycle No. 2, Either Side
CURRENT
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = V
4. Start of valid data depends on which timing becomes effective last t
ADDRESS
DATA
BUSY
DATA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
BUSY has no relationship to valid output data.
BDD
delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
OUT
OUT
OUT
I
CE
OE
I
CC
SS
IH
IH
, CE = V
and OE = V
PREVIOUS DATA VALID
IL
, and is OE = V
IL
, and the address is valid prior to or coincidental with CE transition LOW.
IL
. Address is valid prior to the coincidental with CE transition LOW.
t
OH
t
t
AA
PU
50%
t
LZ
t
(1)
t
ACE
RC
AOE
AOE
t
, t
, t
BDDH
t
LZ
ACE
ACE
t
AOE
(1)
, t
,
t
AA
AA
(2,3)
, and t
(4)
, and
9
t
BDD
BDD
DATA VALID
.
.
Military, Industrial and Commercial Temperature Ranges
VALID DATA
t
(1)
(3)
OH
t
t
PD
HZ
(4)
(2)
t
HZ
50%
(2)
2689 drw 08
2689 drw 09