IDT71V432S5PFG8 IDT, Integrated Device Technology Inc, IDT71V432S5PFG8 Datasheet - Page 2

• Manufacturer Part Number: IDT71V432S5PFG8
• Description: IC SRAM 1MBIT 5NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71V432S5PFG8

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 1M (32K x 32)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71V432S5PFG8

Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
CLK
CS
I/O
A
ADSC
ADSP
ADV
BWE
BW
CE
CS
GW
LBO
OE
V
V
ZZ
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
0
DD
SS
–A
0
0
1
1
–I/O
14
- BW
31
4
Pin Function
(Cache Controller)
(Processor)
Burst Address Advance
Byte Write Enable
Individual Byte
Chip Enable
Clock
Chip Select 0
Chip Select 1
Global Write Enable
Data Input/Output
Linear Burst Order
Output Enable
Power Supply
Ground
Sleep Mode
Address Inputs
Address Status
Address Status
Write Enables
(1)
N/A
N/A
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
Description
Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Sy nchronous Ad dress Status from Cache Controller. ADSC is an active LOW
input that is used to load the address registers with new addresses. ADSC is
NOT GATED by CE.
Synchronous Address Status from Processor. ADSP is an active LOW input that is
used to load the address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to
advance the internal burst counter, co ntrolling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
Synchronous byte write enable gates the byte write inputs BW
LOW at the rising edge of CLK then BW
CLK. If ADSP is HIGH and BW
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
Synchronous byte write enables. BW
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW
Synchronous chip enable. CE is used with CS
IDT71V432. CE also gates ADSP.
made with respect to this input.
Synchronous active HIGH chip select. CS
Sy nchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 8-bit data bytes
enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
sequence is selected. LBO is a static DC input and must not change state while
enabled on the I/O pins. OE is gated internally by a delay circuit driven by CE,
CS
IDT71V432 and toggling back and forth between them using CE, the internal
de lay circuit delays the OE activation of the data output drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode CE,
CS
HIGH the I/O pins are in a high-impedence state.
Ground pins.
down the IDT71V432 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
that is, there is no address advance.
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
with respect to CLK.
This is the clock input to the IDT71V432. All timing referenc es for the device are
the chip.
the chip.
when LOW on the rising edge of CLK. GW supercedes individual byte write
Asynchronous burst order sele ction DC input. When LBO is HIGH the Interleaved
the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are
3.3V power supply inputs.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
0
0
, and CS
, and CS
6.42
2
1
1
. In dual-bank mode, when the user is utilizing two banks of
are all tied active and there is no output enable delay. When OE is
1
Commercial and Industrial Temperature Ranges
–BW
X
is LOW at the rising edge of CLK then data will
4
must meet specified setup and hold times
1
controls I/O(7:0), BW
X
1
0
inputs are passed to the next stage in
is used with CE and CS
is used with CE and CS
0
and CS
1
to enable the
2
controls I/O(15:8),
1
–BW
0
1
4
to enable
to enable
. If BWE is
3104 tbl 02