IDT71V632S5PFG8 IDT, Integrated Device Technology Inc, IDT71V632S5PFG8 Datasheet - Page 8

• Manufacturer Part Number: IDT71V632S5PFG8
• Description: IC SRAM 2MBIT 5NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71V632S5PFG8

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 2M (64K x 32)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 71V632S5PFG8

DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
NOTE:
1. The LBO pin will be internally pulled to V
AC Test Loads
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
3. SA4 speed grade corresponds to a t
4. 0°C to +70°C temperature range only.
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
(Typical, ns)
y S
V
V
y S
I
O
I
I
Δt
O
m
S
I
D
S
Z Z
H
L
1 B
I |
D
B
I |
CD
b
m
I |
L
L
3 (
3 (
LI
l o
Z Z
O
b
I/O
|
3 .
3 .
|
|
Figure 3. Lumped Capacitive Load, Typical Derating
l o
MAX,
) V
) V
O
u S
S
u S
F
u S
F
o P
l u
l u
e p
a t
p p
p p
p p
6
5
4
3
2
1
w
S l
S l
d n
inputs are cycling at the maximum frequency of read cycles of 1/t
i t a r
r e
n I
O
O
O
Z Z
y l
y l
y l
y b
a t
e l
a P
u p
t u
u
u
g n
u S
20 30 50
d n
u C
u C
u C
p e
p t
p t
a
u p
a r
o P
L t
d n
t u
t u
p p
y b
o P
e r r
e r r
e r r
L t
m
M
a e
w
o L
i H
y l
B L
e
o
t n
t n
t n
w
r e
o P
a e
Figure 1. AC Test Load
r e t
e d
a k
h g
Z
w
r e
u C
O
a k
w
0
e g
o V
r e
e r r
o V
n I
e g
= 50Ω
Capacitance (pF)
a P
u p
a t l
t n
u C
a t l
80
a r
u C
e g
L t
e g
e r r
m
e D
e D
e D
V
f
V
f
V
= f
Z Z > V
e r r
100
a e
t n
f =
f =
D
D
D
e
i v
D
i v
D
i v
D
CD
r e t
t n
a k
0
M
M
e c
e c
e c
=
=
=
) 2 (
A
A
e g
of 4.5 ns.
50Ω
X
X
M
M
M
H
DD
) 2 (
) 2 (
S
D
D
D
a
a
a
,
u C
l e
s e
s e
, . x
, . x
, . x
if it is not actively driven in the application and the ZZ pin will be internally pulled to V
V
c e
e T
l e
l e
V
e r r
D
(V
(1)
V
V
V
D
t s
e t
c e
c e
DDQ
t n
N I
N I
N I
=
, d
DD
C
e t
e t
) 1 (
(V
> V
> V
> V
M
n o
, d
, d
O
a
u
/2
HD
. x
i d
H I
H I
H
= 3.3V +10/-5%)
O
O
p t
200
I
I
D
V
V
C > V
O
O
o i t
u
u
s t u
r o < V
r o < V
3619 drw 03
D
D
E
L
H
p t
p t
r o < V
3619 drw 05
D
D
s n
=
= V
=
s t u
s t u
=
=
O
5
5 –
e p
m
M
M
O
O
L I
L I
H I
D L
m
,
,
a
a
, A
e p
e p
DDQ
, n
, . x
, . x
r o E
, A
,
, n
, n
V
O > V
D
V
V
V
D
D
N I =
N I =
D
– 0.2V
=
=
6.42
M
V 0
V 0
o C
M
. n i
2
H I
CYC
0 7
5 1
0 1
8
0 2
. n i
m
,
o t
o t
S
V
AC Test Conditions
e T
. l '
while ADSC = LOW; f=0 means no input lines are changing.
n I
I
I
O
A
4 A
p n
p n
V
V
O
,
t s
u p
u
C
D
D
U
p t
V
3 (
t u
t u
T
D
D
e T
) 4 ,
P t
C
=
t u
n I
LD
i R
i T
n o
—
—
—
—
t s
V 0
l u
. d
i m
i T
e s
i d
e s
o L
i m
g n
= 0.2V)
F /
o t
o i t
g n
d a
e L
l a
e R
V
s n
o C
T l
D
e v
e R
2
I/O
5 6
5 1
0 1
r e f
D
0 0
m
m i
Commercial and Industrial Temperature Ranges
,
s l
Figure 2. High-Impedence Test Load
r e f
. l '
n e
V
s e
D
n e
5 S
e c
D
e c
* Including scope and jig capacitance.
(for t
=
e L
n I
2
M
5 6
5 1
0 1
0 0
351Ω
e L
. d
e v
a
OHZ
. x
e v
s l
s l
, t
o C
CHZ
1
0 6
5 1
0 1
+3.3V
m
0 8
, t
. l '
OLZ
6 S
317Ω
5pF*
, and t
n I
1
0 6
M
5 1
0 1
0 8
2
—
—
—
—
. d
. n i
4 .
SS
DC1)
if not actively driven.
S
o C
e e
1
5 5
3619 drw 04
5 1
0 1
m
0 6
F
0
. l '
g i
M
0
o t
0 3
—
7 S
. 1
. 1
r u
5
5
2
. x a
4 .
s n
V 5
V 5
s e
. 3
n I
V 0
1
5 5
5 1
0 1
1
0 6
. d
a
d n
6 3
6 3
6 3
U
9 1
9 1
9 1
µ
µ
µ
V
V
t i n
U
2
m
m
m
m
A
A
A
l b t
l b t
l b t
t i n
A
A
A
A
3 1
2 1
4 1