M25P16-VME6TG NUMONYX, M25P16-VME6TG Datasheet - Page 19

• Manufacturer Part Number: M25P16-VME6TG
• Description: IC FLASH 16MBIT 75MHZ 8VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P16-VME6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFPN
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 15ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFPN EP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P16-VME6TG; M25P16-VME6TGTR

6.1
6.2
Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Disable (WRDI)
The Write Disable (WRDI) instruction
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Figure 9.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Write Enable (WREN) instruction sequence
Write Disable (WRDI) instruction sequence
S
C
D
Q
S
C
D
Q
High Impedance
0
High Impedance
0
(Figure
(Figure
1
1
2
2
Instruction
Instruction
3
9) resets the Write Enable Latch (WEL) bit.
3
8) sets the Write Enable Latch (WEL) bit.
4
4
5
5
6
6
7
7
AI02281E
AI03750D
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