M25P16-VME6TG NUMONYX, M25P16-VME6TG Datasheet
M25P16-VME6TG
Specifications of M25P16-VME6TG
M25P16-VME6TGTR
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M25P16-VME6TG Summary of contents
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... BP1 and BP2) More than 20 year data retention n Packages n – RoHS compliant December 2008 VFQFPN8 (MP) 6 × (MLP8) SO8N (MN) 150 mils width PDIP8 (BA) 300 mils width Rev 15 M25P16 VDFPN8 (ME (MLP8) SO8W (MW) 208 mils width SO16 (MF) 300 mils width 1/56 www.numonyx.com 2 ...
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December 2008 Rev 15 2/56 2 ...
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... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...
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SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. Power-up timing and V Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10. Operating conditions Table 11. ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. SO8, VFQFPN, VDFPN, and PDIP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Enable (WREN) instruction sequence Figure 9 ...
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... Description The M25P16 Mbit (2 Mbit × 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical Figure 3. SO16 connections Don’t use 2. See Package mechanical 8/56 M25P16 HOLD AI08517 section for package dimensions, and how to identify pin-1. M25P16 HOLD ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). ...
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V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS 10/56 supply voltage. CC ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P16 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 5. SPI modes supported CPOL CPHA ...
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... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P16 features the following data protection mechanisms: Power on reset and an internal timer (t l changes while the power supply is outside the operating specification ...
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... If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Memory content Protected area Figure 6). ...
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Figure 6. Hold condition activation C HOLD 16/56 Hold condition (standard use) (non-standard use) Hold condition AI02029D ...
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... Memory organization The memory is organized as: 2 097 152 bytes (8 bits each sectors (512 Kbits, 65536 bytes each) l 8192 pages (256 bytes each). l Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from but not page erasable. ...
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... Table 3. Memory organization Sector 18/56 Address range 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h 1FFFFFh 1EFFFFh ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...
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Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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... A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). l The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (15h). ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is in progress. ...
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SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction (attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Figure 15. Page Program (PP) instruction sequence Data byte MSB 1. Address bits A23 to A21 are Don’t care. 30/ ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device ...
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... Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the old-style 8-bit electronic signature, whose value for the M25P16 is 14h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit electronic signature that is read by the Read Identifier (RDID) instruction ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit electronic signature, for the M25P16, is 14h. Figure 20. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in still ensures that the device is put into Standby Power mode ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay ...
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... These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Program, Erase and Write commands are rejected by the device ...
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... V Electrostatic discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The minimum voltage may reach the value for no more than 20 ns during transitions. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the ...
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Table 14. DC characteristics Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 Deep Power-down I CC2 current I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I ...
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Table 15. AC characteristics ( Applies only to products made with T9HX technology, identified with process digit ‘4’ Test conditions specified in Symbol Alt. Parameter Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN, ...
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Table 15. AC characteristics ( Applies only to products made with T9HX technology, identified with process digit ‘4’ Symbol Alt. Page Program cycle time (256 bytes) Page Program cycle time (n bytes, where ( ...
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Table 16. AC characteristics (25 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN WRDI, RDSR, WRSR f Clock frequency for READ instructions R ...
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Table 16. AC characteristics (25 MHz operation) (continued) Test conditions specified in Symbol Alt. (5) t Sector Erase cycle time SE (5) t Bulk Erase cycle time must be greater than or equal to 1/ ...
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Figure 24. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL High Impedance Q Figure 25. Hold timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439 tHHCH AI02032 ...
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Figure 26. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 46/56 tCH tCLQV tCL tQLQH tQHQL tSHQZ LSB OUT AI01449e ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Table 17. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data Symbol Typ A 0. 0.65 A3 0.20 b 0.40 D 6.00 D1 5.75 D2 3.40 E 5.00 ...
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Figure 28. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the ...
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Figure 29. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol Typ ...
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Figure 30. SO8W – 8 lead plastic small outline, 208 mils body width, package outline Drawing is not to scale. Table 20. SO8 wide – 8 lead plastic small outline, 208 mils body width, ...
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Figure 31. SO16 wide – 16-lead plastic small outline, 300 mils body width, package outline B SO-H 1. Drawing is not to scale. Table 21. SO16 wide – 16-lead plastic small outline, 300 mils body width, mechanical data Symbol A ...
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Figure 32. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline Package is not to scale. Table 22. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package ...
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... Grade 3 is available only in devices delivered in SO8N packages. Note: For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 μm, process digit ‘4’), please contact your nearest Numonyx Sales Office. 54/56 M25P16 – ...
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... VDFPN8 package updated (see 8-lead very thin dual flat package no lead, 8 × 6 mm, package mechanical data). Note 2 added to scheme. Figure 4: Bus master and memory devices on the SPI bus Note 2 added. SO8N package specifications updated (see Table 19). Small text changes. scheme. and ...
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... Added note 2 and 3 to Table 9: Absolute maximum Modified maximum value for t CLQV technology). Applied Numonyx branding. Added a reference to customer’s ability to request dedicated part number in Section 6.3: Read Identification (RDID) on page Moved specifications in “max” column to “min” column and changed the “ ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...