MT46H32M32LFCM-5 IT:A Micron Technology Inc, MT46H32M32LFCM-5 IT:A Datasheet - Page 48
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MT46H32M32LFCM-5 IT:A
Manufacturer Part Number
MT46H32M32LFCM-5 IT:A
Description
IC DDR SDRAM 1GBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Specifications of MT46H32M32LFCM-5 IT:A
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
1G (32M x 32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Organization
32Mx32
Density
1Gb
Address Bus
13b
Access Time (max)
6.5/5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
150mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Standard Mode Register
Figure 17: Standard Mode Register Definition
Burst Length
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Note:
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency (CL), and operating mode, as shown in Figure 17. Reserved states
should not be used as this may result in setting the device into an unknown state or
cause incompatibility with future versions of LPDDR devices. The standard mode regis-
ter is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is programmed again, until the device
goes into deep power-down mode, or until the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided
it is performed correctly. The mode register must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
quent operation. Violating any of these requirements will result in unspecified operation.
Read and write accesses to the device are burst-oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
1. The integer n is equal to the most significant address bit.
Mn
0
–
...
M10
M
0
–
n + 2
0
0
1
1
M9
0
–
M
M8
n + 1
0
n + 2
0
1
0
1
–
BA1
0
M7
n + 1
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
0
BA0
M6
0
0
0
0
1
1
1
1
Operating Mode
Normal operation
All other states reserved
n
Operating Mode
An ...
M5
...
0
0
1
1
0
0
1
1
48
10
A10
M4
0
1
0
1
0
1
0
1
9
A9
CAS Latency
1Gb: x16, x32 Mobile LPDDR SDRAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
A8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
3
7
A7 A6 A5 A4 A3
CAS Latency BT
6
5
4
M3
0
1
3
Burst Length
Standard Mode Register
t
MRD before initiating the subse-
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
Burst Type
Interleaved
Sequential
M1
1
0
0
1
1
0
0
1
1
0
M0
© 2007 Micron Technology, Inc. All rights reserved.
0
1
0
1
0
1
0
1
Standard mode register (Mx)
Reserved
Reserved
Reserved
Reserved
M3 = 0
Address bus
16
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
M3 = 1
16
2
4
8