MT46H32M16LFBF-5 IT:B Micron Technology Inc, MT46H32M16LFBF-5 IT:B Datasheet - Page 13

• Manufacturer Part Number: MT46H32M16LFBF-5 IT:B
• Description: IC DDR SDRAM 512MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M16LFBF-5 IT:B

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Table 3: VFBGA Ball Descriptions
LDQS, UDQS
RAS#, CAS#,
UDM, LDM
BA0, BA1
DQ[15:0]
DQ[31:0]
DQS[3:0]
Symbol
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
CK, CK#
DM[3:0]
A[12:0]
A[12:0]
WE#
CKE
CS#
output
output
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Description
Clock: CK is the system clock input. CK and CK# are differential
clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and the negative
edge of CK#. Input and output data is referenced to the cross-
ing of CK and CK# (both directions of the crossing).
Clock enable: CKE HIGH activates, and CKE LOW deactivates,
the internal clock signals, input buffers, and output drivers. Tak-
ing CKE LOW enables PRECHARGE power-down and SELF RE-
FRESH operations (all banks idle), or ACTIVE power-down (row
active in any bank). CKE is synchronous for all functions except
SELF REFRESH exit. All input buffers (except CKE) are disabled
during power-down and self refresh modes.
Chip select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank se-
lection on systems with multiple banks. CS# is considered part
of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input data mask: DM is an input mask signal for write data. In-
put data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM balls are input-only, the DM loading is
designed to match that of DQ and DQS balls.
Bank address inputs: BA0 and BA1 define to which bank an AC-
TIVE, READ, WRITE, or PRECHARGE command is being applied.
BA0 and BA1 also determine which mode register is loaded dur-
ing a LOAD MODE REGISTER command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ
or WRITE commands, to select one location out of the memory
array in the respective bank. During a PRECHARGE command,
A10 determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Data input/output: Data bus for x16 and x32.
Data strobe: Output with read data, input with write data. DQS
is edge-aligned with read data, center-aligned in write data. It
is used to capture data.
13
512Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
© 2004 Micron Technology, Inc. All rights reserved.