IS42S32200E-7TLI ISSI, Integrated Silicon Solution Inc, IS42S32200E-7TLI Datasheet - Page 9

• Manufacturer Part Number: IS42S32200E-7TLI
• Description: IC SDRAM 64MBIT 143MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32200E-7TLI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 86-TSOPII
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.5 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 140 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1082; IS42S32200E-7TLI

IS42S32200E, IS45S32200E
TRUTH TABLE – CKE
NOTES:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that t
6. Exiting self refresh at clock edge n will put the device in all banks idle state once t
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
NOTE:
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/12/2010
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those
CURRENT STATE
Power-Down
Self Refresh
Clock Suspend
Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
met).
commands should be issued on clock edges occurring during the t
during t
n+1.
CURRENT STATE
Any
Idle
Row Active
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
previous state was SELF REFRESH).
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
xsr
period.
(6)
(5)
(7)
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
AUTO REFRESH
COMMANDn
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
(1-4)
(11)
(7)
(9)
(9)
(7)
xsr
period. A minimum of two NOP commands must be sent
ACTIONn
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
(10)
(10)
(10)
(10)
(8)
(10)
(10)
xsr
is met. COMMAND INHIBIT or NOP
(8)
(8)
(1-6)
xsr
CS RAS CAS WE
CKEn-1
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
has been met (if the
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
CKEn
cks
H
H
H
H
L
L
L
L
L
L
is
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
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