ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 69

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

Data Sheet
Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin)
Bits
[7:4]
3
2
1
0
Table 79. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin)
Bits
[7:0]
Table 80. Register 0x50—OUTD Falling Edge Setting (OUTD Pin)
Bits
[7:4]
3
2
[1:0]
Table 81. Register 0x51—SR1 Rising Edge Timing (SR1 Pin)
Bits
[7:0]
Bit Name
t
Modulate enable
t
Reserved
Volt-second balance
source selection
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Bit Name
t
7
7
8
8
8
9
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x4D, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
If this bit is set to 1, the OUTD rising edge is selected as the start of the integration period for
volt-second balance.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x50, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x4F, which contains the eight MSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x52, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
between 80 ns and 115 ns when using the SR soft start.
Rev. 0 | Page 69 of 88
PERIOD
PERIOD
PERIOD
PERIOD
− 5 ns.
− 5 ns.
− 5 ns.
− 5 ns. It is recommended that the SR1 rising edge not be set
7
8
edge.
edge.
7
8
edge.
edge.
7
8
time. This value is always used with the eight
time. This value is always used with the eight
8
9
time. This value is always used with the top
time. This value is always used with the top
7
8
7
8
left.
left.
right.
right.
8
7
time. Each LSB corresponds to
time. Each LSB corresponds to
8
9
time. Each LSB corresponds to
time. Each LSB corresponds to
ADP1046A
Rx
Rx
Rx
Rx
and t
and t
and t
and t
Rx
Rx
Rx
Rx
and t
and t
and t
and t
Fx
Fx
Fx
Fx
occur
occur
occur
occur
Fx
Fx
Fx
Fx
of a
of a
of a
of a