ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 19

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

Data Sheet
SYNCHRONOUS RECTIFICATION
SR1 and SR2 are recommended for use as the PWM control
signals when using synchronous rectification. These PWM
signals can be configured much like the other PWM outputs.
An optional soft start can be applied to the synchronous
rectifier PWM outputs. The SR soft start can be programmed
using Register 0x54[1:0].
•
•
The advantage of ramping the SR signals is to minimize the
output voltage step that occurs when the SR FETs are turned
on without a soft start. The advantage of turning the SR signals
completely on immediately is that they can help to minimize
the voltage transient caused by a load step.
Using Register 0x54[1], the SR soft start can be programmed to
occur only once (the first time that the SR signals are enabled)
or every time that the SR signals are enabled, for example, when
the system enters or exits light load mode.
When programming the
correct operation of this function by setting the falling edge of
SR1 (t
setting the falling edge of SR2 (t
edge of SR2 (t
Register 0x0F[7] = 1.
SYNCHRONOUS RECTIFIER (SR) DELAY
The
topologies. Every time a PWM signal crosses the isolation barrier
an additional propagation delay is added due to the isolating
components. The
able delay (0 ns to 315 ns in steps of 5 ns) using Register 0x79[5:0].
This delay moves both SR1 and SR2 later in time to compensate
for the added delay due to the isolating components (see Figure 57).
In this way, the edges of all PWM outputs can be aligned, and
the SR delay can be applied separately as a constant dead time.
ADP1046A
When SR soft start is disabled (Register 0x54[0] = 0),
the SR signals are turned on to their full PWM duty cycle
values immediately.
When SR soft start is enabled (Register 0x54[0] = 1), the
SR signals ramp up from zero duty cycle to the desired
duty cycle in steps of 40 ns per switching cycle.
10
) to a lower value than the rising edge of SR1 (t
11
). SR soft start can also be disabled by setting
is well suited for dc-to-dc converters in isolated
ADP1046A
ADP1046A
allows programming of an adjust-
12
) to a lower value than the rising
to use SR soft start, ensure
9
) and by
Rev. 0 | Page 19 of 88
LIGHT LOAD MODE
The
light load conditions based on the value of CS2. Register 0x3B and
Register 0x7D are used to program the light load mode thresholds
for turn-off and turn-on of SR1, SR2, and other PWM outputs.
Below the light load threshold programmed in Register 0x3B, the
SR outputs are disabled; the user can also program any of the other
PWM outputs to shut down below this threshold. Light load mode
allows the
that incorporate automatic phase shedding at light load.
To prevent the system from oscillating between light load
and normal modes due to the thresholds being programmed
too close to each other, a programmable debounce is provided
in Register 0x7D[5:4]. This debounce prevents the part from
changing state within the programmed interval.
The speed of the SR enable is programmable from 37.5 µs to 300 µs
in four discrete steps using Register 0x7D[3:2]. This ensures that,
in case of a load step, the SR signals (and any other PWM outputs
that are temporarily disabled) can be turned on quickly enough to
prevent damage to the FETs that they are controlling.
The light load mode digital filter is also used during light
load mode.
MODULATION LIMIT
The modulation limit register (Register 0x2E) can be programmed
to apply a maximum duty cycle modulation limit to any PWM
signal, thus limiting the modulation range of any PWM output.
When modulation is enabled, the maximum modulation limit is
applied to all PWM outputs collectively. As shown in Figure 22,
this limit is the maximum time variation for the modulated edges
from the default timing, following the configured modulation
direction. There is no minimum duty cycle limit setting. There-
fore, the user must set the rising edges and falling edges based
on the case with the least modulation.
OUTx
Each LSB in Register 0x2E corresponds to a different time step
size, depending on the switching frequency (see Table 46). The
modulated edges cannot extend beyond one switching cycle.
The GUI provided with the
programming this feature (see Figure 23).
Figure 23. Setting Modulation Limits (Modulation Range Shown by Arrows)
ADP1046A
t
t
Rx
Fx
ADP1046A
can be configured to disable PWM outputs under
Figure 22. Modulation Limit Settings
t
MODULATION_LIMIT
to be used with interleaved topologies
ADP1046A
is recommended for
ADP1046A