IS61C256AL-12TLI-TR ISSI, Integrated Silicon Solution Inc, IS61C256AL-12TLI-TR Datasheet - Page 7

• Manufacturer Part Number: IS61C256AL-12TLI-TR
• Description: IC SRAM 256KBIT 12NS 28TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61C256AL-12TLI-TR

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 256K (32K x 8)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Density: 256Kb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 25mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

IS61C256AL
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
10/23/06
ADDRESS
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
SA
DATA UNDEFINED
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
≥
V
IH
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
1-800-379-4774
PWE1
WC
t
t
PWE2
(1)
WC
(1,2)
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
ISSI
CE_WR2.eps
CE_WR3.eps
®
7