SI6467BDQ-T1 Vishay/Siliconix, SI6467BDQ-T1 Datasheet - Page 9
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SI6467BDQ-T1
Manufacturer Part Number
SI6467BDQ-T1
Description
MOSFET 12V 8.0A 1.05W
Manufacturer
Vishay/Siliconix
Datasheet
1.SI6467BDQ-T1.pdf
(11 pages)
Specifications of SI6467BDQ-T1
Product Category
MOSFET
Transistor Polarity
P-Channel
Drain-source Breakdown Voltage
12 V
Gate-source Breakdown Voltage
+/- 8 V
Continuous Drain Current
6.8 A
Resistance Drain-source Rds (on)
12.5 mOhms
Configuration
Single
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Fall Time
85 ns
Minimum Operating Temperature
- 55 C
Power Dissipation
1.05 W
Rise Time
85 ns
Factory Pack Quantity
3000
Tradename
TrenchFET
Typical Turn-off Delay Time
220 ns
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI6467BDQ-T1-E3
Manufacturer:
VISHAY
Quantity:
12 830
Part Number:
SI6467BDQ-T1-E3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Company:
Part Number:
SI6467BDQ-T1-GE3
Manufacturer:
TI
Quantity:
126
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFET, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET
package footprint. In converting the footprint to the pad set for a
power device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
In the case of the TSSOP-8 package, the thermal connections
are very simple. Pins 1, 5, and 8 are the drain of the MOSFET
for a single MOSFET package and are connected together. In
the dual package, pins 1 and 8 are the two drains. For a
small-signal device or integrated circuit, typical connections
would be made with traces that are 0.020 inches wide. Since
the drain pins also provide the thermal connection to the
package, this level of connection is inadequate. The total
cross section of the copper may be adequate to carry the
current required for the application, but it presents a large
thermal impedance. Also, heat spreads in a circular fashion
from the heat source. In this case the drain pins are the heat
sources when looking at heat spread on the PC board.
Document Number: 70738
17-Dec-03
0.032
0.018
0.45
0.8
FIGURE 1. Single MOSFET TSSOP-8 Pad
0.073
1.78
Mounting LITTLE FOOT
Pattern with Copper Spreading
0.284
7.6
0.118
3.54
0.026
0.66
0.122
3.1
R
TSSOP-8 Power MOSFETs
The pad patterns with copper spreading for the single-MOSFET
TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2)
show the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of copper
overlies the drain pins. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. These patterns
use all the available area underneath the body for this purpose.
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
0.032
0.018
0.45
0.8
FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with
0.073
1.78
Copper Spreading
0.091
1.65
0.284
7.6
Vishay Siliconix
0.026
0.66
AN806
www.vishay.com
0.122
3.1
1