BR93L66RF-WE2 Rohm Semiconductor, BR93L66RF-WE2 Datasheet - Page 9

• Manufacturer Part Number: BR93L66RF-WE2
• Description: IC EEPROM 4KBIT 2MHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR93L66RF-WE2

• Memory Size: 4K (256 x 16)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 2MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Memory Configuration: 256 X 16
• Interface Type: Serial, Microwire
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4) Write enable (WEN) / disable (WDS) cycle
5) Erase cycle timing (ERASE)
6) Chip erase cycle timing (ERAL)
At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid until the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it.
When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
In this command, data of the designated address is made into "1". The data of the designated address becomes
"FFFFh". Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
In this command, data of all addresses is erased. Data of all addresses becomes "FFFFh". Actual ERASE starts at the
fall of CS after the fall of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
DO
DO
CS
SK
DI
DO
CS
SK
CS
SK
DI
DI
High-Z
High-Z
High-Z
Fig. 38 Write enable (WEN) / disable (WDS) cycle
1
1
1
1
1
1
0
1
0
2
2
2
Fig. 40 Chip erase cycle timing
1
0
Fig. 39 Erase cycle timing
0
3
Am
1
4
4
4
0
5
A3
6
ENABLE = 1 1
DISABLE= 0 0
A2
7
A1
8
A0
n
t
t
n
9/16
CS
CS
n
t
t
E/W
E/W
BUSY
BUSY
t
t
STATUS
SV
STATUS
SV
READY
READY
BR93L46-W : n=9
BR93L56/66-W : n=11
BR93L76/86-W : n=13
BR93L46-W : n=9, m=5
BR93L56/66-W : n=11, m=7
BR93L76/86-W : n=13, m=9
BR93L46-W : n=9
BR93L56/66-W : n=11
BR93L76/86-W : n=13