BR93L66RF-WE2 Rohm Semiconductor, BR93L66RF-WE2 Datasheet - Page 10

• Manufacturer Part Number: BR93L66RF-WE2
• Description: IC EEPROM 4KBIT 2MHZ 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BR93L66RF-WE2

• Memory Size: 4K (256 x 16)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOP
• Clock Frequency: 2MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Package /: RoHS Compliant
• Memory Configuration: 256 X 16
• Interface Type: Serial, Microwire
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application
1) Method to cancel each command
2) At standby
READ
WRITE, WRAL
ERASE, ERAL
Standby current
When CS is "L", SK input is "L", DI input is "H", and even with middle electric potential, current does not increase.
Timing
As shown in Fig. 44, when SK at standby is "H", if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to "L" status. (Refer to Fig. 45.)
Fig. 41 READ cancel available timing
Fig. 43 ERASE, ERAL cancel available timing
a : From start bit to 25 clock rise
b : 25 clock rise and after
a : From start bit to 9 clock rise
b : 9 clock rise and after
Start bit
Start bit
Start bit
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Cancel by CS = "L"
Cancel by CS = "L"
1 bit
1 bit
1 bit
Method to cancel : cancel by CS = "L"
CS
SK
DI
*
3
*
2
Fig. 44 Wrong action timing
Fig. 42 WRITE, WRAL cancel available timing
Cancel is available in all areas in read mode.
Ope code
Ope code
Ope code
CS = SK = DI = "H"
Wrong recognition as a start but
2 bits
2 bits
2 bits
*
3
*
Start bit input
2
Address
Address
Address
6 bits
a
a
6 bits
6 bits
*
*
*
1
1
1
SK
DI
SK
DI
tE/W
9 Rise of clock
1/2
b
25 Rise of clock
A1
16 bits
16 bits
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
*2 11 clocks in BR93L56-W, and BR93L66-W
D1
Data
Data
8
10/16
24
Enlarged figure
Address is 10 bits in BR93L76-W, and BR93L86-W.
13 clocks in BR93L76-W, and BR93L86-W
Enlarged figure
A0
D0
9
25
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
Address is 10 bits in BR93L76-W, and BR93L86-W.
(In the case of BR93L46-W)
*1 Address is 8 bits in BR93L56-W, and BR93L66-W.
*2 27 clocks in BR93L56-W, and BR93L66-W
*
3
CS
SK
tE/W
Address is 10 bits in BR93L76-W, and BR93L86-W.
29 clocks in BR93L76-W, and BR93L86-W
DI
*
2
b
Fig. 45 Normal action timing
If CS is started when SK = "L" or DI = "L", a start
bit is recognized correctly.
(In the case of BR93L46-W)
Start bit input