ATSAM4S-EK2 Atmel, ATSAM4S-EK2 Datasheet - Page 32

• Manufacturer Part Number: ATSAM4S-EK2
• Description: Development Boards & Kits - ARM EVAL KIT SAM4S8 & SAM4S16
• Manufacturer: Atmel

Specifications of ATSAM4S-EK2

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: SAM4SD32C
• Core: ARM Cortex M4
• Interface Type: RS-232, USB
• Operating Supply Voltage: 5 V

4.5.6
Table 4-14. JTAG/ICE Connector J6 Signal Descriptions
SAM4S-EK2 User Guide
Pin
10
11
12
13
14
1
2
3
4
5
6
7
8
9
output line, sampled on the rising edge
nTRST TARGET RESET — Active-low
signal, for synchronizing test logic and
TDI TEST DATA INPUT — Serial data
Input Return test clock signal from the
JTAG Debugging Connector J6
TCK TEST CLOCK — Output timing
TDO JTAG TEST DATA OUTPUT —
output signal that resets the target
Serial data output from the target
TMS TEST MODE SELECT
control register access
Vsupply. 3.3V power
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
Figure 4-30. JTAG/ICE Connector J6
VTref. 3.3V power
of the TCK signal
Mnemonic
RTCK
target
GND
GND
GND
GND
GND
GND
Description
This is the target reference voltage. It is used to check if the target has power, to
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to Vdd or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
Common ground.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
Common ground.
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
Common ground.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
Common ground.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
Common ground.
JTAG data output from target CPU. Typically connected to TDO on target CPU.
Common ground.
Evaluation Kit Hardware
11176A–ATARM–24-Sep-12
4-25