ATSAM4S-EK2 Atmel, ATSAM4S-EK2 Datasheet - Page 15

• Manufacturer Part Number: ATSAM4S-EK2
• Description: Development Boards & Kits - ARM EVAL KIT SAM4S8 & SAM4S16
• Manufacturer: Atmel

Specifications of ATSAM4S-EK2

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: SAM4SD32C
• Core: ARM Cortex M4
• Interface Type: RS-232, USB
• Operating Supply Voltage: 5 V

4.3.8.3
4.3.9
SAM4S-EK2 User Guide
Touch Screen Interface
JTAG/ICE
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device
on the SAM4SD32 SPI bus. The controller sends back the information about the X and Y positions, as
well as a measurement for the pressure applied to the touch panel. The touch panel can be used with
either a stylus or a finger.
The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two
interrupt signals are connected and provide events information back to the microcontroller: PenIrq and
Busy.
For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect
either end driver from the other:
For further information, refer to the
Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test points (TP8, TP9) for optional
function extension.
Figure 4-10. Touch Panel Control
A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK2 for the connection of a com-
patible ARM JTAG emulator interface, such as the SAM-ICE from Segger.
On the touch panel controller side, R67 and R69.
On ZigBEE side, R117 and R120.
Note:
Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD
PenIrq (PA16) is shared with ZigBEE signal IRQ0.
Busy (PA17) is shared with ZigBEE signal IRQ1.
Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take
care not to have both drivers enabled at the same time on either PA16 or PA17.
2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M4 is
module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from
this system reset signal.
not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to
floating input, the internal pull-up resistor corresponding to this PIO line must be
enabled.
TP8
AGND_TP
R72
100K
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
TP9
R73
100K
“Schematics”
LCD TOUCH SCREE N
2
3
4
5
7
8
MN7
ADS7843E
XP
YP
XM
YM
IN3
IN4
PENIRQ
DOUT
BUSY
DCLK
VREF
VCC1
VCC2
GND
DIN
CS
16
14
12
15
13
11
9
1
10
6
section.
PA14
PA13
PA12
+3V3
C58
100nF
R67
R70
R62
100K
AGND_TP
JP32
Header2
C59
100nF
0R
0R
PA11
PA17
C60
100nF
+3V3
R71
1R
C61
4.7uF
R65
100K
L2
10uH-100mA
R69 0R
R74
0R
PA16
DGND
+3V3
Evaluation Kit Hardware
11176A–ATARM–24-Sep-12
4-8