EVAL-SSM2537Z Analog Devices, EVAL-SSM2537Z Datasheet

EVAL-SSM2537Z

Manufacturer Part Number

EVAL-SSM2537Z

Description

Audio IC Development Tools SSM2537 EVALUATION BOARD

Manufacturer

Analog Devices

Type

Class D Audio Amplifiersr

Series

SSM2537r

Datasheet

1.EVAL-SSM2537Z.pdf (16 pages)

Specifications of EVAL-SSM2537Z

Rohs

yes

Product

Evaluation Boards

Tool Is For Evaluation Of

SSM2537

Operating Supply Voltage

2.5 V to 5.5 V

Factory Pack Quantity

Current page: 1 of 16
Download datasheet (328Kb)

Data Sheet

FEATURES

Filterless digital Class-D amplifier

Pulse density modulation (PDM) digital input interface

2.7 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply

Available in 9-ball, 1.2 mm × 1.2 mm, 0.4 mm pitch WLCSP

93% efficiency into 8 Ω at full scale

Output noise: 25 µV rms at 3.6 V, A-weighted

THD + N: 0.005% at 1 kHz, 100 mW output power

PSRR: 80 dB at 217 Hz, with dither input

Quiescent power consumption: 5.1 mW

Pop-and-click suppression

Configurable with PDM pattern inputs

Short-circuit and thermal protection with autorecovery

Smart power-down when PDM stop condition or no clock

64 × f

DC blocking high-pass filter and static input dc protection

User-selectable ultralow EMI emissions and low latency modes

Power-on reset (POR)

Minimal external passive components

APPLICATIONS

Mobile handsets

GENERAL DESCRIPTION

The

that offers higher performance than existing DAC plus Class-D

solutions. The

where system noise can corrupt the small analog signal sent to

the amplifier, such as mobile phones and portable media players.

The

(DAC), a power amplifier, and a PDM digital interface on a single

chip. The integrated DAC plus analog sigma-delta (Σ-Δ) modulator

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

with <1% total harmonic distortion plus noise (THD + N)

(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 µH load)

input detected

SSM2537

or 128 × f

is a PDM digital input Class-D power amplifier

combines an audio digital-to-analog converter

SSM2537

operation supporting 3 MHz and 6 MHz clocks

is ideal for power sensitive applications

PDAT

PCLK

INTERFACE

POWER-ON

RESET

INPUT

Document Feedback

FUNCTIONAL BLOCK DIAGRAM

CLOCKING POWER

FILTERING/

CONTROL

VDD

DAC

Figure 1.

MODULATOR

GAIN_FS

CLASS-D

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

Σ-Δ

architecture enables extremely low real-world power consumption

from digital audio sources with excellent audio performance. Using

the SSM2537, audio can be transmitted digitally to the audio

amplifier, significantly reducing the effect of noise sources such

as GSM interference or other digital signals on the transmitted

audio. The

ous output power with <1% THD + N driving a 4 Ω load from a

5.0 V supply.

The

scheme that requires no external LC output filters. The closed-loop,

three-level modulator design retains the benefits of an all-digital

amplifier, yet enables very good PSRR and audio performance. The

modulation continues to provide high efficiency even at low output

power and has an SNR of 102 dB PDM input. Spread-spectrum

pulse density modulation is used to provide lower EMI-radiated

emissions compared with other Class-D architectures.

The

pin that can select two different gain settings, optimized for 3.6 V

and 5 V operation. This same pin controls the internal digital fil-

tering and clocking, which can be set for a 64 × f

sample rate to support both 3 MHz and 6 MHz PDM clock rates.

The

shutdown current of 1.6 µA for both power supplies. Shutdown is

enabled automatically by gating input clock and data signals. A

standby mode can be entered by applying a designated PDM stop

condition sequence. The device also includes pop-and-click sup-

pression circuitry. This suppression circuitry minimizes voltage

glitches at the output when entering or leaving the low power

state, reducing audible noises on activation and deactivation.

The

of −40°C to +85°C. It has built-in thermal shutdown and output

short-circuit protection. It is available in a 9-ball, 1.2 mm ×

1.2 mm wafer level chip scale package (WLCSP).

2.7 W Class-D Audio Amplifier

SSM2537

PDM Digital Input, Mono

POWER STAGE

PVDD

has a four-state gain and sample frequency selection

FULL-BRIDGE

features a high efficiency, low noise modulation

has a micropower shutdown mode with a typical

is specified over the industrial temperature range

SSM2537

LRSEL

PGND

is capable of delivering 2.7 W of continu-

OUT+

OUT–

SSM2537

or 128 × f

www.analog.com

input

Related parts for EVAL-SSM2537Z

EVAL-SSM2537Z Summary of contents

Page 1

... Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...

Page 2

SSM2537 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Digital Input/Output Specifications........................................... 4 PDM Interface Digital Timing Specifications .......................... 5 Absolute Maximum Ratings ...

Page 3

Data Sheet SPECIFICATIONS PVDD = 5.0 V, VDD = 1 128× when f = 64×, PDM clock = 3.072 MHz. S Table 1. Parameter DEVICE CHARACTERISTICS Output Power Total Harmonic Distortion Plus Noise Efficiency Average ...

Page 4

SSM2537 Parameter Supply Current, Modulator Standby Current Shutdown Current NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter INPUT SPECIFICATIONS Input Voltage High PCLK, PDAT, LRSEL Pins Input Voltage Low PCLK, PDAT, LRSEL Pins Input Leakage ...

Page 5

Data Sheet PDM INTERFACE DIGITAL TIMING SPECIFICATIONS Table 3. Limit Parameter t MIN Timing Diagram PCLK LEFT PDAT DATA t Unit Description MAX 10 ns Clock fall time 10 ns ...

Page 6

SSM2537 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 4. Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility OUT− and OUT+ Pins Storage Temperature Range Operating Temperature Range Junction Temperature ...

Page 7

Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Function A1 PDAT Input A2 LRSEL Input A3 OUT− Output B1 VDD Supply B2 PVDD Supply B3 PGND Ground C1 PCLK Input C2 GAIN_FS Input ...

Page 8

SSM2537 TYPICAL PERFORMANCE CHARACTERISTICS 100 = 8Ω + 33µ 64× PVDD = 2.5V 0.1 0.01 0.001 0.001 0.01 0.1 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 8 Ω, ...

Page 9

Data Sheet 100 = 8Ω + 33µ PVDD = 2. 64× 0.1 0.25W 0.0625W 0.01 0.125W 0.001 10 100 1k FREQUENCY (Hz) Figure 10. THD + N vs. Frequency, PVDD = 2.5 V, ...

Page 10

SSM2537 100 = 8Ω + 33µ PVDD = 2. 128× 0.1 0.25W 0.01 0.0625W 0.125W 0.001 10 100 1k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, PVDD = 2 ...

Page 11

Data Sheet 2.0 = 8Ω + 33µ 64× 1.8 S 1.6 1.4 1.2 1.0 THD = 10% 0.8 THD = 1% 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) Figure 22. Maximum Output ...

Page 12

SSM2537 100 90 80 PVDD = 3.6V PVDD = 2. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 OUTPUT POWER (W) Figure 28. Efficiency vs. Output Power into 4 Ω, ...

Page 13

Data Sheet THEORY OF OPERATION MASTER CLOCK The SSM2537 requires a clock present at the PCLK input pin to operate. This clock must be fully synchronous with the incoming digital audio on the serial interface. Clock frequencies must fall into ...

Page 14

... Most of the time, however, the output differential voltage due to the Analog Devices, Inc., three-level, Σ-Δ output modulation. This feature ensures that the current flowing through the inductive load is small. ...

Page 15

Data Sheet APPLICATIONS INFORMATION LAYOUT As output power increases, take care to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops ...

Page 16

... ORDERING GUIDE Model 1 Temperature Range SSM2537ACBZ-R7 −40°C to +85°C SSM2537ACBZ-RL −40°C to +85°C EVAL-SSM2537Z RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10981-0-10/12(0) 1.240 1.200 SQ 1.160 3 0 ...

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