AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 40

• Manufacturer Part Number: AT25DF641-S3H-T
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.
11.1.
40
Other Commands and Functions
Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than
wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete
normally. The Reset command allows a program or erase operation in progress to be ended abruptly and returns
the device to an idle state. Since the need to reset the device is immediate, the Write Enable command does not
need to be issued prior to the Reset command being issued. Therefore, the Reset command operates
independently of the state of the WEL bit in the Status Register.
The Reset command can only be executed if the command has been enabled by setting the Reset Enabled
(RSTE) bit in the Status Register to a logical “1”. If the Reset command has not been enabled (the RSTE bit is in
the logical “0” state), then any attempts at executing the Reset command will be ignored.
To perform a Reset, the
address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately
after the opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the
Since the program or erase operation may not complete before the device is reset, the contents of the page being
programmed or the block being erased cannot be guaranteed to be valid.
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown
Registers, or the SPRL, RSTE, and SLE bits in the Status Register. The WEL, PS, and ES bits, however, will be
reset back to their default states. If a Reset operation is performed while a sector is erase suspended, the
suspend operation will abort, and the contents of the block being erased in the suspended sector will be left in an
undefined state. If a Reset is performed while a sector is program suspended, the suspend operation will abort,
and the contents of the page that was being programmed and subsequently suspended will be undefined. The
remaining pages in the 64-Kbyte sector will retain their previous contents.
The complete opcode and confirmation byte must be clocked into the device before the
the
will be performed.
Figure 11-1. Reset
Atmel AT25DF641
CS
SCK
SO
CS
pin is deasserted, the program or erase operation currently in progress will be terminated within a time of t
CS
SI
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation
MS B
HIG H-IMP E DANC E
1
0
1
1
CS
1
2
OPCODE
pin must first be asserted and the opcode of F0h must be clocked into the device. No
1
3
0
4
0
5
0
6
0
7
MS B
1
CONFIR MATION BYTE IN
8
1
9
0
10 11
1
0
12
0
13
0
14 15
0
CS
pin is deasserted, and
3680F–DFLASH–4/10
RST
.