AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 11

• Manufacturer Part Number: AT25DF641-S3H-T
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.
3680F–DFLASH–4/10
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by f
To perform the Dual-Output Read Array operation, the
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address
bytes, a single dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data
being output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO
pin while bit six of the same data byte will be output on the SIO pin. During the next clock cycle, bits five and four
of the first data byte will be output on the SO and SIO pins, respectively. The sequence continues with each byte
of data being output after every four clock cycles. When the last byte (7FFFFFh) of the memory array has been
read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
Deasserting the
state. The
Figure 6-4.
SCK
CS
SO
SI
CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Dual-Output Read Array
CS
MS B
HIG H-IMP E DANC E
0
0
pin will terminate the read operation and put the SO and SIO pins into a high-impedance
0
1
1
2
OP C ODE
1
3
1
4
0
5
1
6
1
7
MS B
A
8
A
9
ADDR E S S B ITS A23-A0
A
10 11
A
A
12
A
CS
A
29 30
pin must first be asserted and the opcode of 3Bh must
A
A
31 32
MS B
X
X
33
DON'T C AR E
X
34
X
35
X
36
X
37 38
Atmel AT25DF641
X
X
39
MS B
D
D
DAT A B Y T E 1
40
6
7
OUT P UT
D
D
41
4
5
D
D
42 43
2
3
D
D
0
1
DAT A B Y T E 2
D
D
44
6
7
OUT P UT
D
D
45
4
5
D
D
46
2
3
D
D
47 48
0
1
MS B
D
D
6
7
D
D
4
5
RDDO
11
.