AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet - Page 32

• Manufacturer Part Number: AT25DF641-S3H-T
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
Table 9-4.
The user-programmable portion of the OTP Security Register does not need to be erased before it is
programmed. In addition, the Program OTP Security Register command operates on the entire 64-byte user-
programmable portion of the OTP Security Register at one time. Once the user-programmable space has been
programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it
is not possible to only program the first two bytes of the register and then program the remaining 62-bytes at a
later time.
Before the Program OTP Security Register command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To program the OTP Security Register,
the
address bytes denoting the first byte location of the OTP Security Register to begin programming at. Since the
size of the user-programmable portion of the OTP Security Register is 64-bytes, the upper order address bits do
not need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their
values can be either a logical “1” or “0”. After the address bytes have been clocked in, data can then be clocked
into the device and will be stored in the internal buffer.
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register
memory space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations
to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the
64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For
example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device,
then the first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh
while the last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security
Register (addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state
(FFh). In addition, if more than 64-bytes of data are sent to the device, then only the last 64-bytes sent will be
latched into the internal buffer.
When the
appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number
of data bytes sent to the device. If less than 64-bytes of data were sent to the device, then the remaining bytes
within the OTP Security Register will not be programmed and will remain in the erased state (FFh).
programming of the data bytes is internally self-timed and should take place in a time of t
suspend the programming of the OTP Security Register.
The three address bytes and at least one complete byte of data must be clocked into the device before the
is deasserted, and the
device will abort the operation and the user-programmable portion of the OTP Security Register will not be
programmed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security
Register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent,
the
Security Register was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting
the t
Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.
Atmel AT25DF641
CS
CS
OTPP
0
pin being deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP
pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three
time to determine if the data bytes have finished programming. At some point before the OTP Security
CS
OTP Security Register
pin is deasserted, the device will take the data stored in the internal buffer and program it into the
One-Time User Programmable
1
CS
pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
. . .
62
Security Register
63
Byte Number
64
Factory Programmed by Atmel
65
. . .
OTPP
. It is not possible to
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3680F–DFLASH–4/10
127
CS
The
pin