AT25DF161-SH-B Atmel, AT25DF161-SH-B Datasheet - Page 3

• Manufacturer Part Number: AT25DF161-SH-B
• Description: IC FLASH 16MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF161-SH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (2M x 8)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 16Mb
• Access Time (max): 5ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Mounting Style: SMD/SMT
• Memory Configuration: 8192 Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3687E–DFLASH–11/10
2.
Table 2-1.
Symbol
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
V
GND
CC
Pin Descriptions and Pinouts
Pin Descriptions
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device
will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the
SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on
the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is
required to end an operation. When ending an internally self-timed operation such as a program or
erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always latched
in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge
of SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into the device. The SI
pin is used for all data input including command and address sequences. Data on the SI pin is always
latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow two bits
of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To maintain
consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout the document
with exception to sections dealing with the Dual-Output Read Array command in which it will be
referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data out from the device.
Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to allow
two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK. To maintain
consistency with SPI nomenclature, the SOI pin will be referenced as SO throughout the document
with exception to sections dealing with the Dual-Input Byte/Page Program command in which it will
be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
“Protection Commands and Features” on page 18
pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not
be used. However, it is recommended that the WP pin also be externally connected to V
possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin
will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to
start. A Hold condition pauses serial communication only and does not have an effect on internally self-
timed operations such as a program or erase cycle. Please refer to
details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to V
possible.
DEVICE POWER SUPPLY: The V
Operations at invalid V
GROUND: The ground reference for the power supply. GND should be connected to the system
ground.
CC
voltages may produce spurious results and should not be attempted.
CC
pin is used to supply the source voltage to the device.
for more details on protection features and the WP
“Hold” on page 39
CC
whenever
for additional
CC
whenever
Atmel AT25DF161
Asserted
State
Low
Low
Low
-
-
-
-
-
Input/Output
Output/Input
Power
Power
Type
Input
Input
Input
Input
3