AT45DB021D-SH-T Atmel, AT45DB021D-SH-T Datasheet - Page 6

• Manufacturer Part Number: AT45DB021D-SH-T
• Description: IC FLASH 2MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB021D-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (1024 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the
array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
maximum SCK frequency allowable for the Continuous Array Read is defined by the f
Continuous Array Read bypasses the data buffer and leaves the contents of the buffer unchanged.
Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz
This command can be used with the serial interface to read the main memory array sequentially without a dummy
byte up to maximum frequencies specified by f
264-bytes, the CS must first be asserted then an opcode, 03H, must be clocked into the device followed by three
address bytes (which comprise the 24-bit page and byte address sequence). The first 10-bits (PA9 - PA0) of the
19-bit address sequence specify which page of the main memory array to read, and the last nine bits (BA8 - BA0)
of the 19-bit address sequence specify the starting byte address within the page. To perform a continuous read
with the page size set to 256-bytes, the opcode, 03H, must be clocked into the device followed by three address
bytes (A17 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being
output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When
the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading
at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from
the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the
array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
Continuous Array Read bypasses the data buffer and leaves the contents of the buffer unchanged.
Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 2,048-pages in the main
memory, bypassing the data buffer and leaving the contents of the buffer unchanged. To start a page read from the
Atmel
three address bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes. The
first 10-bits (PA9 - PA0) of the 19-bit address sequence specify the page in main memory to be read, and the last
9-bits (BA8 - BA0) of the 19-bit address sequence specify the starting byte address within that page. To start a
page read from the binary page size (256-bytes), the opcode D2H must be clocked into the device followed by
three address bytes and four don’t care bytes. The first 10-bits (A17 - A8) of the 18-bit sequence specify which
page of the main memory array to read, and the last 8-bits (A7 - A0) of the 18-bit address sequence specify the
starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the
read operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO
(serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue
reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read
operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page
Read is defined by the f
contents of the buffer unchanged.
Buffer Read
The SRAM data buffer can be accessed independently from the main memory array, and utilizing the Buffer Read
Command allows data to be sequentially read directly from the buffer. Two opcodes, D4H or D1H, can be used for
the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency that will be used to
Atmel AT45DB021D
®
DataFlash
®
standard page size (264-bytes), an opcode of D2H must be clocked into the device followed by
SCK
specification. The Main Memory Page Read bypasses the data buffer and leaves the
CAR2
. To perform a continuous read array with the page size set to
CAR1
specification. The
3638J–DFLASH–5/10