AT45DB021D-SH-T Atmel, AT45DB021D-SH-T Datasheet - Page 32

• Manufacturer Part Number: AT45DB021D-SH-T
• Description: IC FLASH 2MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB021D-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (1024 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.
32
Figure 16-2. Output Test Load
AC Waveforms
Six different timing waveforms are shown on
makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low
transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as
t
Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to
waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t
timing waveforms are valid over the full frequency range (maximum frequency = 66MHz) of the RapidS serial case.
Figure 17-1. Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)
Figure 17-2. Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz)
WL
SCK
SCK
Atmel AT45DB021D
SO
SO
CS
CS
SI
SI
). Timing waveforms 1 and 2 conform to Atmel
DEVICE
UNDER
TEST
HIGH IMPEDANCE
HIGH Z
t
CSS
t
SU
t
t
CSS
V
t
SU
VALID IN
t
WL
30pF
VALID IN
VALID OUT
t
WH
t
WH
t
V
t
HO
t
H
t
H
t
WL
VALID OUT
t
HO
t
page
CSH
t
CSH
®
32. Waveform 1 shows the SCK signal being low when CS
RapidS
HIGH IMPEDANCE
t
t
DIS
HIGH IMPEDANCE
t
CS
t
DIS
CS
™
serial interface but for frequencies up to 66MHz.
WL
3638J–DFLASH–5/10
period. These