ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 16

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ISPPAC-POWR1208-01T44E

Manufacturer Part Number
ISPPAC-POWR1208-01T44E
Description
Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
Manufacturer
Lattice
Datasheet

Specifications of ISPPAC-POWR1208-01T44E

Number Of Voltages Monitored
12
Monitored Voltage
Adjustable
Undervoltage Threshold
1.03 V
Overvoltage Threshold
5.72 V
Manual Reset
Not Resettable
Watchdog
No Watchdog
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
800
Supply Current (typ)
15000 uA
Supply Voltage - Min
2.25 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-POWR1208-01T44E
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
16, 32, 64, 128, 256 and 512 (Table 3). After the clock for the timers is divided down, it is used to drive the program-
mable timers. The four timers share the same timer clock frequency but may have different end count values. The
timers can cover a range from 32us to 524ms for the internal oscillator. Longer delays can be achieved by using the
external clock as an input.
Table 3. Timer Values
For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the
appropriate delays in an easy-to-select menu format.
The control inputs for Timer1-Timer4 can be driven by any of the 16 PLD macrocell outputs. The reset for the timers
is a function of the Global Reset pin (RESET), a power-on reset or when the timer gate goes low. The waveforms in
Figure 6 show the basic timer start and reset functions. Timer and clock divider values are entered in during the
design phase using PAC-Designer software, simple pull-down menus allow the user to select the clocking mode
and the values for the timers and the PLD clock.
Figure 6. Timer Waveforms
1. Timer values based on 250kHz clock.
0.032 ms
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
62 kHz
÷ ÷ ÷ ÷ 4
Timer Gate
Timer Output
(From PLD)
(To PLD)
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
31.2 kHz
2.048ms
÷ ÷ ÷ ÷ 8
1
Timer
Start
16.384 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
15.6 kHz
2.048ms
÷ ÷ ÷ ÷ 16
ProgrammableTimer
Timer Period
Delay
16.384 ms
32.768 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
7.8 kHz
÷ ÷ ÷ ÷ 32
Expired
Timer
16
16.384 ms
32.768 ms
65.536 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
3.9 kHz
Reset
Timer
÷ ÷ ÷ ÷ 64
Timer
Start
131.072 ms
16.384 ms
32.768 ms
65.536 ms
ispPAC-POWR1208 Data Sheet
1.024 ms
4.096 ms
8.192 ms
2.048ms
2 kHz
÷ ÷ ÷ ÷ 128
ProgrammableTimer
Timer Period
Delay
131.072 ms
262.144 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
2.048ms
1 kHz
÷ ÷ ÷ ÷ 256
Expired
Timer
131.072 ms
262.144 ms
524.288 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
0.5 kHz
÷ ÷ ÷ ÷ 512

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