ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 15

• Manufacturer Part Number: ISPPAC-POWR1208-01T44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR1208-01T44E

• Number Of Voltages Monitored: 12
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 800
• Supply Current (typ): 15000 uA
• Supply Voltage - Min: 2.25 V

Lattice Semiconductor
Clock and Timer Systems
Figure 5 shows a block diagram of the ispPAC-POWR1208’s internal clock and timer systems. The PLD clock can
be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz.
Figure 5. Clock and Timer Block
Table 2. PLD Clock Prescaler
The internal oscillator runs at a fixed frequency of 250kHz. This main signal is then fed to the PLD clock pre-scaler
and also the Timer Clock pre-scaler (Figure 5). For the PLD Clock, the main 250kHz oscillator is divided down to
eight selectable frequencies shown in the Table 2. The architecture of the clock network allows the PLD clock to be
driven to the CLK pin. This enables the user access to the PLD clock as an output for expansion mode or other
uses of the (CLK) clock pin.
Schematically, when the switch is in the upper position, the internal oscillator drives the PLD clock pre-scaler and
the timer pre-scaler. In this mode, the CLK pin is an open-drain output and represents the same frequency as the
PLD clock. This is used when operating other devices (such as “slave” sequencing devices) in a synchronized
mode. When the switch is in the lower position, the CLK pin is an input and must be driven with an external clock
source. When driven from an external source, the same PLD clock pre-scaler is available to this external clock. The
frequencies available for the PLD clock will be the external clock frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128,
depending on the programmable value chosen.
The Timer Clock Pre-Scaler divides the internal 250kHz oscillator (or external clock, if selected) down before it gen-
erates the clock for the four programmable timers. The pre-scaler has eight different divider ratios: Divide by 4, 8,
1. Values based on 250kHz clock.
PLD Clock Frequency (kHz)
250kHz
Internal
OSC
CLK
1
62.5
31.3
15.6
250
125
7.8
3.9
2
(Time Out Range)
Timer Prescaler
PLD Clock
Prescaler
15
PLD Prescaler Divider
128
16
32
64
1
2
4
8
ispPAC-POWR1208 Data Sheet
Timer1
Timer2
Timer3
Timer4