ISPPAC-POWR1208-01T44E Lattice, ISPPAC-POWR1208-01T44E Datasheet - Page 13

• Manufacturer Part Number: ISPPAC-POWR1208-01T44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR1208-01T44E

• Number Of Voltages Monitored: 12
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 800
• Supply Current (typ): 15000 uA
• Supply Voltage - Min: 2.25 V

Lattice Semiconductor
product term allocation array greatly expands the PLD’s ability to implement complex logical functions by allowing
logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions.
The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. The combinatorial func-
tions are achieved through the bypass MUX function shown. By having the polarity control XOR, the logic reduction
can be best fit to minimize the number of product terms. The flip-flop’s clock is driven from a common clock that can
be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports
asynchronous reset and preset functions, derived from either product terms, the global reset input or the power-on
reset signal.
Figure 3. ispPAC-POWR1208 Macrocell Block Diagram
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product Term
Global Polarity Fuse for
Init Product Term
Product Term Allocation
Global Reset
13
Power On Reset
Macrocell flip-flop provides
ispPAC-POWR1208 Data Sheet
D, T, or combinatorial
output with polarity
D/T
R
CLK
P
Q
To ORP